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1. 发明专利

JP2010183036A Semiconductor device and manufacturing method therefor 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010183036A
公开(公告)日：2010-08-19
申请号：JP2009027807
申请日：2009-02-09
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI
IPC分类号： H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a vertical ferroelectric capacitor that has reduced damages on a ferroelectric film, and a manufacturing method therefor.
SOLUTION: The semiconductor device includes a semiconductor substrate 11; a transistor 13 having a diffusion layer 16 made of either a source or a drain that is mutually separately disposed on the semiconductor substrate 11; an electrode 35 that extends nearly vertically in a direction perpendicular to the surface of the semiconductor substrate 11 and is connected to the diffusion layer 16 via a contact plug 19; an electrode 36 that faces the electrode 35, extends substantially vertically in the perpendicular direction to the surface of the semiconductor substrate 11, and is connected to the diffusion layer 16 via the contact plug 19; a ferroelectric film 33, having both surfaces that face each other and contact the electrode 35 of electrode 36, respectively; and a seed film 23 that is disposed on the transistor 13 side to contact the ferroelectric film 33 and contacts either the electrode 35 or the electrode 36 that face each other.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有降低铁电体膜损伤的垂直铁电电容器的半导体器件及其制造方法。解决方案：半导体器件包括半导体衬底11; 具有由半导体基板11上相互分离设置的源极或漏极构成的扩散层16的晶体管13; 电极35，其在与半导体基板11的表面垂直的方向上大致垂直地延伸，并通过接触插塞19连接到扩散层16; 面向电极35的电极36在与半导体基板11的表面垂直的方向上大致垂直地延伸，并且经由接触插塞19连接到扩散层16; 两个表面彼此面对并分别与电极36的电极35接触的铁电体膜33; 以及种子薄膜23，其设置在晶体管13侧以与铁电体膜33接触并接触彼此相对的电极35或电极36。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009099644A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009099644A
公开(公告)日：2009-05-07
申请号：JP2007267441
申请日：2007-10-15
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI , KUMURA YOSHINORI
IPC分类号： H01L21/8246 , H01L21/768 , H01L23/522 , H01L27/10 , H01L27/105
CPC分类号： H01L27/11507 , G11C11/22 , H01L27/105 , H01L27/11509 , H01L28/55 , H01L28/65
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device improved in a yield without degrading characteristics; and to provide a method of manufacturing the same.
SOLUTION: The semiconductor device 100 comprises: a substrate 10; a first insulating layer 33 formed over the substrate 10; lower contact holes 34 formed through the first insulating layer 33; a plurality of first plug electrodes 35 each formed inside the contact hole 34 to the surface of the insulating layer 33; a capacitor layer formed in a first region A on the first plug electrode 35; and second plug electrodes 39 formed in second regions B, on the first plug electrode 35, different from the first region A. The capacitor layer includes a lower electrode 15, a ferroelectric film 16, and an upper electrode 17 which are sequentially stacked. The first plug electrode 35 includes a plug conductive layer 351 formed from the surface of the substrate 10, and a plug barrier layer 352 formed from above the plug conductive layer 351 up to an upper surface of the first insulating layer 33, and having a higher etching selection ratio than the lower electrode 15.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种在不降低特性的情况下提高成品率的半导体器件; 并提供其制造方法。解决方案：半导体器件100包括：衬底10; 形成在基板10上的第一绝缘层33; 通过第一绝缘层33形成的下接触孔34; 多个第一插头电极35，每个形成在接触孔34内部至绝缘层33的表面; 形成在第一插头电极35上的第一区域A中的电容器层; 以及形成在第一插头电极35上的与第一区域A不同的第二区域B中的第二插头电极39.电容器层包括依次堆叠的下电极15，铁电体膜16和上电极17。第一插头电极35包括从基板10的表面形成的插头导电层351和从插头导电层351的上方形成直到第一绝缘层33的上表面的插塞阻挡层352，并且具有较高的蚀刻选择比率低于下电极15.版权所有：（C）2009，JPO＆INPIT

3. 发明专利

JP2008078417A Semiconductor memory device and manufacturing method thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2008078417A
公开(公告)日：2008-04-03
申请号：JP2006256268
申请日：2006-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11507 , G11C11/22 , G11C11/223 , H01L27/11502 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To reduce a capacitor leak current by reducing damage of a side wall of a semiconductor memory device such as FeRAM or MRAM. SOLUTION: A semiconductor device is provided with a source-drain diffusion layer 26 of a switching transistor disposed on a semiconductor substrate 10; an interlayer insulating film 8 disposed on the semiconductor substrate 10 and the source-drain diffusion layer 26; and a ferroelectric capacitor consisting of a lower electrode 14 disposed on the interlayer insulating film 8, a ferroelectric film 16 disposed on the lower electrode 14 and an upper electrode 18 disposed on the ferroelectric film 16. In this device, an angle α formed between a side wall where the upper electrode 18 contacts the ferroelectric film 16 and the surface of the ferroelectric film 16 is larger than an angle β formed between a hard mask side wall 20 near the surface of the upper electrode 18 and the surface of the ferroelectric film 16. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过减少诸如FeRAM或MRAM的半导体存储器件的侧壁的损坏来减小电容器漏电流。解决方案：半导体器件设置有设置在半导体衬底10上的开关晶体管的源极 - 漏极扩散层26; 设置在半导体衬底10和源极 - 漏极扩散层26上的层间绝缘膜8; 以及由设置在层间绝缘膜8上的下电极14，配置在下电极14上的强电介质膜16和配置在强电介质膜16上的上电极18构成的铁电电容器。在该装置中，上电极18与强电介质膜16接触的侧壁和铁电体膜16的表面比形成在上电极18的表面附近的硬掩模侧壁20与强电介质膜16的表面之间的角度β大版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2013201387A Three-dimensional transistor and method of manufacturing the same 审中-公开
标题翻译：三维晶体管及其制造方法
公开(公告)号：JP2013201387A
公开(公告)日：2013-10-03
申请号：JP2012070149
申请日：2012-03-26
申请人： Toshiba Corp , 株式会社東芝
发明人： HOSOYA KEIJI , KANETANI HIROYUKI , YAGISHITA JUNJI , MITSUI DAISUKE
IPC分类号： H01L21/336 , H01L21/20 , H01L21/265 , H01L21/76 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a three-dimensional transistor that allows reducing the influence of lateral-direction growth due to facet formation and film thickness variation of an epitaxial layer at a pattern edge associated with selective epitaxial silicon growth.SOLUTION: A three-dimensional transistor includes: a semiconductor substrate having a top surface in which a crystal plane direction is (100); an element isolation region formed in the semiconductor substrate and partitioning an element region on the top surface; a gate electrode formed on the element region of the semiconductor substrate via a gate insulating film and in which gate insulating side walls are provided on side surfaces; a source/drain region formed in the element region of the semiconductor substrate in a self-alignment manner with respect to the gate electrode; and a selective epitaxial silicon layer formed on the source/drain region by epitaxial growth. A first side surface portion of the selective epitaxial silicon layer on the element isolation region side has a curved surface shape.
摘要翻译：要解决的问题：提供三维晶体管，其能够减少由于与选择性外延硅生长相关联的图案边缘处的外延层的刻面形成和膜厚度变化引起的横向生长的影响。解决方案：三维晶体管包括：具有晶面方向为（100）的顶表面的半导体衬底; 形成在所述半导体衬底中并分隔所述顶表面上的元件区域的元件隔离区; 栅电极，其经由栅极绝缘膜形成在所述半导体衬底的元件区域上，并且在侧表面上设置有栅极绝缘侧壁; 在所述半导体衬底的元件区域中相对于所述栅电极自对准的方式形成源极/漏极区域; 以及通过外延生长在源/漏区上形成的选择性外延硅层。元件隔离区域侧上的选择性外延硅层的第一侧表面部分具有曲面形状。

5. 发明专利

JP2011155268A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2011155268A
公开(公告)日：2011-08-11
申请号：JP2011034436
申请日：2011-02-21
申请人： Toshiba Corp , 株式会社東芝
发明人： NATORI KATSUAKI , KANETANI HIROYUKI , YAMAKAWA KOJI
IPC分类号： H01L27/105 , C23C14/08 , C23C16/40 , C23C16/42 , H01L21/316 , H01L21/8246
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric capacitor which is free of damage in a post-step and has superior characteristics.
SOLUTION: The method of manufacturing the semiconductor device includes a first step of forming capacitors (200, 300 and 400), each formed by sandwiching a dielectric film between a lower electrode and an upper electrode, over a semiconductor substrate, a second step of forming oxide films (122, 125, and 128) covering the capacitors (200, 300 and 400) by a CVD method using O
3 and TEOS as raw materials, and a third step of forming Al
2 O
3 (123, 126, and 129) as protective films on the oxide films (122, 125, and 128) by an ALD method.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供在后续步骤中没有损坏并具有优异特性的铁电电容器。解决方案：制造半导体器件的方法包括：形成电容器（200,300和400）的第一步骤，每个电容器（200,300和400）通过在半导体衬底上夹在下电极和上电极之间而形成，电介质膜通过使用O 3 SBS和TEOS作为原料的CVD法形成覆盖电容器（200,300,400）的氧化膜（122,125和128）的步骤，以及形成Al （123,126和129）作为氧化膜（122,125和128）上的保护膜，通过ALD方法。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2011138903A Semiconductor device, and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011138903A
公开(公告)日：2011-07-14
申请号：JP2009297630
申请日：2009-12-28
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI
IPC分类号： H01L27/105 , H01L21/8246
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same which can suppress reduction of an MgO film while improving polarization characteristics of a ferroelectric capacitor.
SOLUTION: The semiconductor device includes a switching transistor 301, first and second diffusion layers 121
1 , 121
2 , an interlayer insulation film 131, the MgO film 141, the ferroelectric capacitor 201 having a lower electrode 211 formed on the MgO film, a ferroelectric film 212, and an upper electrode 213, a first plug 171 formed on the upper electrode 213, a second plug 172 formed on the first diffusion layer, and a third plug 173 formed on the second diffusion layer and electrically conducting the lower electrode 211 and the second diffusion layer. The third plug 173 includes a barrier metal layer 181 for forming a side surface and bottom surface, and a plug material layer 182 formed on the barrier metal layer 181. The barrier metal layer 181 is interposed between the MgO film 141 and the plug material layer 182.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以在提高铁电电容器的极化特性的同时抑制MgO膜的还原的半导体器件及其制造方法。解决方案：半导体器件包括开关晶体管301，第一和第二扩散层121，第一和第二扩散层121，层间绝缘膜131，MgO膜141，具有形成在MgO膜上的下电极211，强电介质膜212和上电极213的铁电电容器201，形成在上电极213上的第一插塞171，形成在第一扩散层上的第二插塞172，第三插头173形成在第二扩散层上并导电下电极211和第二扩散层。第三插头173包括用于形成侧表面和底表面的阻挡金属层181和形成在阻挡金属层181上的插塞材料层182.阻挡金属层181介于MgO膜141和插塞材料层之间 182.版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2011029400A Ferroelectric memory 审中-公开
标题翻译：电磁记忆
公开(公告)号：JP2011029400A
公开(公告)日：2011-02-10
申请号：JP2009173500
申请日：2009-07-24
申请人： Toshiba Corp , 株式会社東芝
发明人： KANETANI HIROYUKI
IPC分类号： H01L27/105 , H01L21/8246
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a ferroelectric memory. SOLUTION: The ferroelectric memory includes: a field effect transistor 2 having diffusion layers 23, 24 provided in a semiconductor substrate 50 and a gate electrode 21 provided on a channel region between the diffusion layers 23, 24 via a gate insulating film; contact plugs 30, 31 buried in an interlayer insulating film 51 and provided on the diffusion layers 23, 24; an oxidation prevention film 40 provided on the interlayer insulating film 51 and on the contact plugs 30, 31; a capacitor 1 including a ferroelectric film 10 provided on the oxidation prevention film 40 and electrodes 11, 12 provided on the contact plugs 30, 31 while penetrating the ferroelectric film 10 and oxidation prevention film 40; and a seed layer 41 provided on the oxidation prevention film 40 between the electrodes 11, 12 and functioning a seed crystal for the ferroelectric film 10. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提高铁电存储器的可靠性。铁电存储器包括：具有设置在半导体衬底50中的扩散层23,24和通过栅极绝缘膜设置在扩散层23,24之间的沟道区上的栅电极21的场效应晶体管2; 埋置在层间绝缘膜51中并设置在扩散层23,24上的接触插塞30,31; 设置在层间绝缘膜51和接触塞30,31上的防氧化膜40; 包括设置在防氧化膜40上的强电介质膜10和设置在接触插塞30,31上的电极11,12，同时穿透铁电体膜10和防氧化膜40; 以及设置在电极11,12之间的氧化防止膜40上的籽晶层41，并且用于铁电体膜10的晶种。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2010182889A Semiconductor memory device and method for fabricating the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2010182889A
公开(公告)日：2010-08-19
申请号：JP2009025390
申请日：2009-02-05
申请人： Toshiba Corp , 株式会社東芝
发明人： NISHIMURA JUN , KUMURA YOSHINORI , KANETANI HIROYUKI , OZAKI TORU
IPC分类号： H01L21/8246 , H01L27/105
CPC分类号： H01L27/11507 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a ferrodielectric film of good crystallinity and a method for fabricating the same.
SOLUTION: The semiconductor memory device includes a single semiconductor substrate, a field effect transistor formed on the semiconductor substrate, an inter-layer insulating film formed on the field effect transistor and the semiconductor substrate, a plug having a single-crystalline structure, the plug being formed in the inter-layer insulating film and being connected with either of a source/drain region of the field effect transistor, a lower electrode having a single-crystalline structure formed on the plug, a ferrodielectric film formed on the lower electrode, and an upper electrode formed on the ferrodielectric film.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有良好结晶度的铁电膜的半导体存储器件及其制造方法。解决方案：半导体存储器件包括单个半导体衬底，形成在半导体衬底上的场效应晶体管，形成在场效应晶体管和半导体衬底上的层间绝缘膜，具有单晶结构所述插塞形成在所述层间绝缘膜中并且与所述场效应晶体管的源极/漏极区域中的任一个连接，形成在所述插塞上的具有单晶结构的下部电极，形成在所述下部绝缘膜上的铁电体膜电极和形成在铁电体膜上的上电极。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2010135543A Fabricating method of nonvolatile semiconductor storage apparatus 有权
标题翻译：非挥发性半导体存储装置的制造方法
公开(公告)号：JP2010135543A
公开(公告)日：2010-06-17
申请号：JP2008309634
申请日：2008-12-04
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUI YUKITERU , KUBOTA TAKEO , TATEYAMA YOSHIKUNI , MINAMI YOSHIHIRO , KANETANI HIROYUKI
IPC分类号： H01L21/8246 , H01L27/105
CPC分类号： H01L27/11507 , H01L21/0206 , H01L21/31053 , H01L21/32139 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To reduce etching failure of a ferroelectric material, caused by the dust on a hard mask. SOLUTION: After stacking an electrode film 23, a ferroelectric film 24, and an electrode film 25 sequentially on a semiconductor substrate 11, a hard mask HM is stacked. Then, by using a surfactant, the surface of the hard mask HM is scrub-cleaned, and thereafter, the hard mask HM is patterned in compliance with the planar shape of a ferroelectric capacitor 26. By anisotropically etching the electrode film 25, the ferroelectric film 24, and the electrode film 23 and sequentially using the patterned hard mask HM, a top electrode 25a, a ferroelectric layer 24a, and the bottom electrode 23a of the ferroelectric capacitor 26 are formed on the semiconductor substrate 11. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：减少由硬掩模上的灰尘引起的铁电材料的蚀刻失效。解决方案：在半导体衬底11上依次层叠电极膜23，铁电体膜24和电极膜25之后，堆叠硬掩模HM。然后，通过使用表面活性剂，对硬质掩模HM的表面进行擦洗处理，然后根据强电介质电容器26的平面形状将硬掩模HM图案化。通过各向异性蚀刻电极膜25，铁电体膜24和电极膜23，并依次使用图案化硬掩模HM，上电极25a，强电介质层24a和强电介质电容器26的底电极23a形成在半导体衬底11上。版权所有：（C）2010，JPO＆INPIT

10. 发明专利

JP2010129962A Semiconductor memory device, and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2010129962A
公开(公告)日：2010-06-10
申请号：JP2008306317
申请日：2008-12-01
申请人： Toshiba Corp , 株式会社東芝
发明人： OKADA TAKAYUKI , KANETANI HIROYUKI
IPC分类号： H01L21/8246 , H01L27/105
CPC分类号： H01L27/11521 , H01L28/84
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device which improves controllability of concavo-convex formation of a lower electrode of a ferroelectric capacitor, and to provide a method of manufacturing the same.
SOLUTION: The semiconductor memory device has a ferroelectric capacitor FC including: the lower electrode LE formed so as to possess a plurality of projections 20; a ferroelectric film FE formed on the lower electrode; and an upper electrode UE formed on the ferroelectric film.
COPYRIGHT: (C)2010,JPO&INPIT

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