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1. 发明专利

JP2015022330A メモリ制御回路およびプロセッサ有权
标题翻译：存储控制电路和处理器
公开(公告)号：JP2015022330A
公开(公告)日：2015-02-02
申请号：JP2013147508
申请日：2013-07-16
申请人：株式会社東芝 , Toshiba Corp
发明人： NOMURA KUMIKO , FUJITA SHINOBU , ABE KEIKO , IKEGAMI KAZUTAKA , NOGUCHI HIROKI , TAKEDA SUSUMU
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/0802 , G06F1/26 , G06F1/32 , G06F12/0897 , G06F2212/1028 , G06F2212/222 , G06F2212/60 , G06F2212/601 , G11C11/1697 , Y02D10/13
摘要：【課題】オペレーティングシステムによる電力管理以外の手法で、キャッシュメモリの効率的な電力制御を行う。【解決手段】メモリ制御回路は、n(nは2以上の整数)次のキャッシュメモリのうち不揮発性メモリを備えた特定のメモリに対して、他のメモリから読み出しおよび書き込みの要求を行っていない期間が所定時間以上継続したか否かを判定する要求判定部と、前記要求判定部の判定結果に基づいて、前記特定のメモリに対する電源遮断のタイミングを制御する電源制御部と、を備える。【選択図】図1
摘要翻译：要解决的问题：通过除操作系统的电源管理之外的方法对高速缓冲存储器进行有效的功率控制。解决方案：存储器控制电路包括：请求确定单元，确定包括非易失性存储器的特定存储器的周期第n级高速缓冲存储器中的存储器，其中n是等于或大于2的整数，不传送从/向另一存储器读/写数据的请求，持续预定时间或更长时间; 以及电源控制单元，其基于所述请求确定单元的确定结果来控制切断对所述特定存储器的电流供应的定时。

2. 发明专利

JP2013190970A Cache device 有权
标题翻译：缓存设备
公开(公告)号：JP2013190970A
公开(公告)日：2013-09-26
申请号：JP2012056359
申请日：2012-03-13
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMURA KUMIKO , FUJITA SHINOBU , ABE KEIKO , IKEGAMI KAZUTAKA , NOGUCHI HIROKI
IPC分类号： G06F12/08
CPC分类号： G06F1/3275 , G06F1/32 , G06F1/3225 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： PROBLEM TO BE SOLVED: To provide a cache device capable of reducing power consumption while securing performance.SOLUTION: A cache device according to the embodiment, which is a cache device of an n(n≥2)-way set associative system, includes a cache memory, an access control part, and a power control part. The cache memory has a plurality of memory areas corresponding to a plurality of ways on a one-to-one basis. The access control part controls access to the memory area. The power control part controls power supply for each memory area one by one, and controls, as to a memory area to which access control is not executed for a fixed period of time, a power supplied to the memory area to a standby power indicative of a value lower than an operation power at which the memory area is operable. The power control part also controls a standby power of a memory area to which an access control is highly likely to be performed, to a value closer to an operation power than the standby power of a memory area to which an access control is not likely to be performed.
摘要翻译：要解决的问题：提供一种能够在确保性能的同时降低功耗的缓存装置。解决方案：根据本实施例的缓存装置，其是n（n≥2）组合关联系统的高速缓存装置，包括高速缓冲存储器，访问控制部分和功率控制部分。高速缓冲存储器具有与多个方式对应的多个存储区域，该多个存储区域是一对一的。访问控制部件控制对存储器区域的访问。功率控制部分逐个地控制每个存储区域的电源，并且对于在一段固定的时间段内不执行访问控制的存储器区域，控制向存储区域提供指示低于存储区域可操作的操作功率的值。功率控制部分还将访问控制极有可能被执行的存储区域的待机功率控制到比访问控制不太可能的存储区域的待机功率更接近操作功率的值被执行。

3. 发明专利

JP2011054646A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2011054646A
公开(公告)日：2011-03-17
申请号：JP2009200278
申请日：2009-08-31
申请人： Toshiba Corp , 株式会社東芝
发明人： ABE KEIKO , YASUDA SHINICHI , FUJITA SHINOBU
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable ion conduction memory device by reducing rewriting power as much as possible.
SOLUTION: The device includes a layer having ion conductivity, a first electrode formed of a conductive material including a first metal supplied to a layer having ion conductivity as a movable ion and a second electrode formed of a conductive material which does not include the first metal. A resistance value in a low resistance state is set to be a tunnel resistance value between a tip of a metal filament which is brought into contact with the second electrode and is formed between the first electrode and the second electrode, and the first electrode. The resistance value is controlled by a content of the metal supplied to the layer having ion conductivity as the movable ion.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过尽可能减小重写能力来提供高度可靠的离子传导存储器件。解决方案：该器件包括具有离子传导性的层，由导电材料形成的第一电极，该导电材料包括提供给具有离子传导性的层作为可移动离子的第一金属和由不包括的导电材料形成的第二电极第一金属。将低电阻状态下的电阻值设定为与第二电极接触并形成在第一电极和第二电极之间的金属丝的末端与第一电极之间的隧道电阻值。电阻值由提供给具有离子传导性层的金属的含量作为可移动离子来控制。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2008103044A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路设备
公开(公告)号：JP2008103044A
公开(公告)日：2008-05-01
申请号：JP2006286210
申请日：2006-10-20
申请人： Toshiba Corp , 株式会社東芝
发明人： HAMADA MOTOTSUGU , HIRAI TAKATOMO , NAKAMURA SHIHO , MORISE HIROSHI , ABE KEIKO
IPC分类号： G11C13/00
CPC分类号： G11C13/00 , G11C5/14 , G11C13/004 , G11C13/0069 , G11C14/009 , G11C2013/0042 , G11C2013/0054 , G11C2013/0073
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device easily operated as a nonvolatile flip-flop. SOLUTION: This device 100 is provided with a sense amplifier circuit 1, a first variable resistance element 2 where a current equal to a predetermined current value or more flows in a first direction to increase a resistance value, and the current equal to the predetermined current value or more flows in a second direction opposite the first direction to reduce the resistance value, a second variable resistance element 3 where a current equal to a predetermined value or more flows in the second direction to increase a resistance value, and the current equal to the predetermined value or more flows in the first direction to reduce the resistance value, a current path switching circuit 4 for writing data in the first and second variable resistance elements 2 and 3, and an SR flip-flop 5 where data stored in the first and second variable resistance elements 2 and 3 are read by the sense amplifier circuit 1 to be entered. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供容易操作为非挥发性触发器的半导体集成电路器件。解决方案：该装置100设置有读出放大器电路1，第一可变电阻元件2，其中等于预定电流值或更大的电流在第一方向上流动以增加电阻值，并且电流等于预定的电流值以上的电流值沿与第一方向相反的第二方向流动以降低电阻值;第二可变电阻元件3，其中等于或大于预定值的电流在第二方向上流动以增加电阻值;以及等于预定值或以上的电流在第一方向上流动以降低电阻值;电流路径切换电路4，用于在第一和第二可变电阻元件2和3中写入数据;以及SR触发器5，其中存储数据在第一和第二可变电阻元件2和3中被读出放大器电路1读入以进入。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006173555A Switching element, line switching device and logic circuit 有权
标题翻译：开关元件，线路开关器件和逻辑电路
公开(公告)号：JP2006173555A
公开(公告)日：2006-06-29
申请号：JP2005092288
申请日：2005-03-28
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA SHINOBU , ABE KEIKO
IPC分类号： H01L45/00 , H01L49/02
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/008 , H01L45/06 , H01L45/085 , H01L45/1206 , H01L45/1213 , H01L45/1226 , H01L45/1286 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1633 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a switching element used for a crossbar circuit, etc., which achieves the reduction of electric power consumption and miniaturization. SOLUTION: This switching element is for switching on/off operations, and comprises a pair of electrodes 21 and 22 arranged on a substrate with a distance from each other, a phase transformation film 23 provided while being in contact with these electrodes 21 and 22 whose resistance value varies depending on a heating history, and a heating mechanism 25 heating the phase transformation film. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供用于横向电路等的开关元件，其实现了电力消耗的降低和小型化。解决方案：该开关元件用于接通/断开操作，并且包括布置在彼此间隔距离的基板上的一对电极21和22，在与这些电极21接触的同时设置的相变膜23 电阻值根据加热历史而变化的加热机构25以及加热相变膜的加热机构25。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2014191835A Magnetic memory 有权
标题翻译：磁记忆
公开(公告)号：JP2014191835A
公开(公告)日：2014-10-06
申请号：JP2013063764
申请日：2013-03-26
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI HIROKI , ABE KEIKO , FUJITA SHINOBU
IPC分类号： G11C11/15
CPC分类号： G11C11/1675 , G11C7/12 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1693
摘要： PROBLEM TO BE SOLVED: To provide a magnetic memory capable of suppressing consumption.SOLUTION: The magnetic memory comprises: a plurality of memory cells including a first MTJ element with first and second terminals, and a first selection section having third to fifth terminals with the third terminal connected to the first terminal of the first MTJ element and selecting the first MTJ element based on a row selection signal; a word line provided corresponding to each row of the plurality of memory cells, connected to the fifth terminal of the first selection section of the memory cell in the corresponding row, and transmitting the row selection signal to the first selection section; and an equalizer circuit provided between a pair of first and second bit lines so as to correspond to each column of the plurality of memory cells, operating based on a control signal, and moving electric charge of one bit line of the first and second bit lines to the other bit line.
摘要翻译：要解决的问题：提供一种能够抑制消耗的磁存储器。解决方案：磁存储器包括：多个存储单元，包括具有第一和第二端子的第一MTJ元件，以及具有第三至第五端子的第一选择部分，连接到第一MTJ元件的第一端子的第三端子，并且基于行选择信号选择第一MTJ元件; 与所述多个存储单元的每一行对应地设置的字线，连接到所述对应行中的存储单元的第一选择部的第五端子，并将所述行选择信号发送到所述第一选择部; 以及均衡器电路，设置在一对第一和第二位线之间，以便对应于多个存储单元的每列，基于控制信号进行操作，并且移动第一和第二位线的一个位线的电荷到另一个位线。

7. 发明专利

JP2013218403A Cache system 有权
标题翻译：缓存系统
公开(公告)号：JP2013218403A
公开(公告)日：2013-10-24
申请号：JP2012086356
申请日：2012-04-05
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMURA KUMIKO , FUJITA SHINOBU , ABE KEIKO , IKEGAMI KAZUTAKA , NOGUCHI HIROKI
IPC分类号： G06F12/08
CPC分类号： G06F1/3206 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： PROBLEM TO BE SOLVED: To store data by using a nonvolatile memory and reduce power consumption.SOLUTION: A cache system 4 includes: a tag storage unit 10 that is comprised of a volatile memory, has a plurality of ways, and stores a tag for each line; a data storage unit 11 that is comprised of a nonvolatile memory, has a plurality of ways, stores data for each line, and includes a plurality of sense amplifiers SA for reading data; a comparison circuit 12 that compares a tag included in an address with a tag read from the tag storage unit 10; and a controller 13 that turns off the power supply to the sense amplifiers SA for ways that are not accessed, on the basis of the comparison result of the comparison circuit 12.
摘要翻译：要解决的问题：通过使用非易失性存储器存储数据并降低功耗。解决方案：缓存系统4包括：标签存储单元10，其由易失性存储器组成，具有多种方式，并且存储用于每行由非易失性存储器组成的数据存储单元11具有多路，存储每行的数据，并且包括用于读取数据的多个读出放大器SA; 将包括在地址中的标签与从标签存储单元10读取的标签进行比较的比较电路12; 以及控制器13，其基于比较电路12的比较结果，关闭对读出放大器SA的电源的未被访问的方式。

8. 发明专利

JP2013030249A Semiconductor integrated circuit and processor 有权
标题翻译：半导体集成电路和处理器
公开(公告)号：JP2013030249A
公开(公告)日：2013-02-07
申请号：JP2011166070
申请日：2011-07-28
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA SHINOBU , ABE KEIKO
IPC分类号： G11C11/15
CPC分类号： G11C14/0054 , G11C11/16 , G11C14/0081
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile SRAM that suppresses performance degradation and an increase in a circuit area.SOLUTION: A semiconductor integrated circuit according to one embodiment of the present invention includes: a first inverter; a second inverter of which an input terminal is connected to an output terminal of the first inverter and an output terminal is connected to an input terminal of the first inverter; a first transistor of which one end is connected to a first bit line and the other end is connected to the input terminal of the first inverter; a first element group that includes a plurality of transistors disposed between the output terminal of the first inverter and a second bit line; and a second element group that includes a plurality of transistors and a magnetic resistance change element disposed between the output terminal of the second inverter and a first terminal to which a predetermined potential is applied according to operation or between the first transistor and the first terminal.
摘要翻译：要解决的问题：提供抑制性能劣化和电路面积增加的非易失性SRAM。解决方案：根据本发明的一个实施例的半导体集成电路包括：第一反相器; 第二反相器，其输入端子连接到第一反相器的输出端子，输出端子连接到第一反相器的输入端子; 第一晶体管，其一端连接到第一位线，另一端连接到第一反相器的输入端; 第一元件组，其包括设置在第一反相器的输出端子和第二位线之间的多个晶体管; 以及第二元件组，其包括多个晶体管和设置在第二反相器的输出端子与根据操作或第一晶体管和第一端子之间施加预定电位的第一端子之间的磁阻变化元件。版权所有（C）2013，JPO＆INPIT

9. 发明专利

JP2013030024A Information processing device 有权
标题翻译：信息处理设备
公开(公告)号：JP2013030024A
公开(公告)日：2013-02-07
申请号：JP2011166072
申请日：2011-07-28
申请人： Toshiba Corp , 株式会社東芝
发明人： ABE KEIKO , FUJITA SHINOBU
IPC分类号： G06F12/08 , G06F12/06
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/13 , Y02D10/14
摘要： PROBLEM TO BE SOLVED: To provide an information processing device capable of attaining fast access while saving the electric power for a memory.SOLUTION: The information processing device according to an embodiment of the invention comprises: a CPU; a plurality of memory blocks including nonvolatile memories; an internal voltage generation circuit connected to the plurality of memory blocks; switches which are provided corresponding to the internal voltage generation circuit and the plurality of memory blocks respectively, and connect and disconnect a power supply; a power supply control data register which stores a data set for ON/OFF control over the switches; and a power supply control data management circuit which sets the data set in the power supply control data register. The power supply control data management circuit generates the data set for turning ON the switch connected to the internal voltage generation circuit and turning OFF the switch connected to the plurality of memory blocks when a clock signal input to the CPU turns OFF, and sets the data set in the power supply control data register.
摘要翻译：要解决的问题：提供一种能够在保存用于存储器的电力的同时实现快速访问的信息处理装置。解决方案：根据本发明实施例的信息处理设备包括：CPU; 多个存储块，包括非易失性存储器; 连接到所述多个存储块的内部电压产生电路; 开关，其分别与内部电压产生电路和多个存储块相对应地设置，并且连接和断开电源; 电源控制数据寄存器，其存储用于开关上的ON / OFF控制的数据组; 以及电源控制数据管理电路，其将设置在电源控制数据寄存器中的数据设置。电源控制数据管理电路在输入到CPU的时钟信号变为OFF时，生成接通连接到内部电压产生电路的开关的接通数据，并断开与多个存储器块连接的开关，并设定数据设置在电源控制数据寄存器中。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2012203487A Cache system and processor 有权
标题翻译：缓存系统和处理器
公开(公告)号：JP2012203487A
公开(公告)日：2012-10-22
申请号：JP2011065271
申请日：2011-03-24
申请人： Toshiba Corp , 株式会社東芝
发明人： NOMURA KUMIKO , ABE KEIKO , FUJITA SHINOBU
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/123 , G06F2212/225 , Y02B60/1225 , Y02D10/13
摘要： PROBLEM TO BE SOLVED: To provide a cache system of a fast operation and low power consumption.SOLUTION: The cache system according to an embodiment of this invention comprises: a volatile cache memory; a nonvolatile cache memory; an order preservation part for storing data corresponding to the number of pieces of data whose non-use time is longer (or shorter) than that of the data stored in the volatile cache memory that are stored in the nonvolatile cache memory, corresponding to the respective pieces of data stored in the volatile cache memory; and a control part for storing first data stored in the volatile cache memory in the nonvolatile cache memory when it can be determined that the non-use time of the first data is shorter than the non-use time of one of the data stored in the nonvolatile cache memory, on the basis of the data stored in the order preservation part corresponding to the first data when overwriting the first data with second data having another address.
摘要翻译：要解决的问题：提供快速操作和低功耗的缓存系统。解决方案：根据本发明实施例的缓存系统包括：易失性高速缓存存储器; 非易失性高速缓存; 订单保存部分，用于存储对应于非易失性高速缓冲存储器中存储的非易失性高速缓冲存储器中存储的非使用时间长于（或更短）的非使用时间的数据的数量的数据的数据，存储在易失性高速缓冲存储器中的数据段; 以及控制部分，用于当可以确定第一数据的不使用时间比存储在第一数据中的数据之一的不使用时间短时，将存储在易失性高速缓冲存储器中的第一数据存储在非易失性高速缓冲存储器中基于存储在与第一数据对应的订单保存部分中的数据的非易失性高速缓冲存储器，当用具有另一地址的第二数据重写第一数据时。版权所有（C）2013，JPO＆INPIT

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