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1. 发明专利

JPS63184364A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63184364A
公开(公告)日：1988-07-29
申请号：JP1522387
申请日：1987-01-27
申请人： TOSHIBA CORP
发明人： KOMATSU SHIGERU
IPC分类号： H01L29/73 , H01L21/285 , H01L21/3213 , H01L21/331 , H01L29/732
摘要： PURPOSE:To simplify a complex process when an aperture for forming an emitter is drilled by a method wherein the selective etching properties of N-type and P-type polycrystalline silicon to reduce the number of masks. CONSTITUTION:After a resist pattern is left on an SiO2 layer 23, a laminated layer composed of an SiO2 layer 13, an Si3N4 layer 14, 1st polycrystalline silicon layer 15 and the SiO2 layer is patterned by RIE. After the SiO2 layer 23 is removed by an NH4F solution, 2nd polycrystalline silicon layer 16 is formed. Then, As, an N-type impurity, is diffused into the 2nd polycrystalline silicon layer 16 contacted with the 1st polycrystalline silicon layer 15 to convert a part of the 2nd polycrystalline silicon layer 16 into an N-type region 26. In this heat treatment process, boron which is added to the 2nd polycrystalline silicon layer 16 is diffused into silicon to form a diffused layer 18 for leading out the base electrode of a transistor. Then, after an SiO2 layer 33 is removed, the N-type region 26 in the 2nd polycrystalline silicon layer 16 and the 1st polycrystalline silicon layer 15 are dissolved and removed by KOH solution. Then an SiO2 layer 43 is formed on the 2nd polycrystalline silicon layer 16. The SiO2 layer 43 is formed so as to have a thickness of not less than 2000 Angstrom which is four times of the thickness of the SiO2 layer 13 in order to be sufficiently left when the SiO2 layer 13 on the region where an emitter region is to be formed is removed in a process afterwards.

2. 发明专利

JPS61164262A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61164262A
公开(公告)日：1986-07-24
申请号：JP621685
申请日：1985-01-17
申请人： TOSHIBA CORP
发明人： KOMATSU SHIGERU
IPC分类号： H01L29/73 , H01L21/20 , H01L21/225 , H01L21/285 , H01L21/331 , H01L29/423 , H01L29/732
摘要： PURPOSE:To form a bipolar type semiconductor device with high speed or improved high frequency capacity by means of reducing base resistance remarkably. CONSTITUTION:Polycrystalline silicon films 8' are utilized both as buffers be tween single crystal silicon layers MoSi2 films 4' serving as excellent ohmic contacts and diffusion sources forming P type external base regions 14. In other words, even if most part of base region lead-out electrode comprising polycrystalline silicon films 8' and MoSi2 film patterns 4' is composed of the MoSI2 film patterns 4' hardly assuring excellent ohmic contact with the single crystal silicon layers, excellent ohimc contact may be assured by the polycrystalline silicon films 8' laid between the patterns 4' and the base regions 14. Moreover the base resistance may be reduced remarkably since the most part of base region lead-out electrode is composed of the MoSi2 film patterns 4' with less sheet resistance value.

3. 发明专利

JPS6140057A Semiconductor device and manufacture therefor 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS6140057A
公开(公告)日：1986-02-26
申请号：JP16051884
申请日：1984-07-31
申请人： Toshiba Corp
发明人： KOMATSU SHIGERU , ITO TAKAO , KATSUMATA YASUHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
CPC分类号： H01L29/66272
摘要： PURPOSE:To improve performance of a semiconductor device at a high rate or a high frequency, by reducing a base resistance using a laminated structure of a non-single-crystal Si film and a metal silicide film as a base taking out electrode. CONSTITUTION:After an N type buried region 2 is formed in a P type Si substrate 1, an N type epitaxial layer 3 and a field oxidation film 4 are formed. Next, a polycrystal Si film which has been patterned and doped with B is deposited, and moreover an MoSi2 film is deposited thereon. Next, over the entire face, an oxidation film 8 is deposited. Next, using a photo resist pattern 9 formed as a mask, the films 8-6 are etched away to form a base taking out electrode 10. Thereafter, B which is being doped in the films 7, 6 is diffused with heat-treatment to form a P type external base region 12. Moreover, by implanting B, a P type active base region 13 is formed. After an oxidation film 14 is deposited over the entire face, the oxidation film 14' on the side walls of the electrode 10 is left with anisotropic etching. Next, an N type emitter region 16 is formed in the region 13.
摘要翻译：目的：通过使用非单晶Si膜和金属硅化物膜的层叠结构作为基极取出电极来降低基极电阻，来提高高速率或高频率的半导体器件的性能。构成：在P型Si衬底1中形成N +型掩埋区2之后，形成N型外延层3和场氧化膜4。接下来，沉积已经图案化并掺杂有B的多晶Si膜，并且还沉积有MoSi 2膜。接下来，在整个表面上沉积氧化膜8。接下来，使用形成为掩模的光刻胶图案9，将膜8-6蚀刻掉以形成取出电极10的基底。此后，被掺杂在膜7,6中的B被热处理扩散形成P +型外部基极区域12.此外，通过注入B，形成P型有源基极区域13。在整个表面上沉积氧化膜14之后，电极10的侧壁上的氧化膜14'留下各向异性蚀刻。接下来，在区域13中形成N +型发射极区域16。

4. 发明专利

JPS5933860A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS5933860A
公开(公告)日：1984-02-23
申请号：JP14371982
申请日：1982-08-19
申请人： Toshiba Corp
发明人： KOMATSU SHIGERU
IPC分类号： H01L21/8222 , H01L21/22 , H01L21/225 , H01L21/331 , H01L27/082 , H01L29/08 , H01L29/73
CPC分类号： H01L21/82285 , H01L21/2257 , H01L27/0826 , H01L29/0804
摘要： PURPOSE: To form n type regions which have accurate different diffusion depths in one thermally diffusing step by differentiating the ratio of densities of phosphorus and arsenic of n type diffused regions.
CONSTITUTION: n
+ type buried layers A
1 , A
2 and n type insular regions C
1 , C
2 are respectively formed in regions to be formed with transistors T
1 , T
2 of a substrate 20. A polycrystalline silicon 13, to which P and As of the prescribed densities are added at a ratio of P/As=32, is covered on the overall surface of the substrate 20. The second insulating layer 14 such as oxidized silicon is covered on the overall surface of the substrate 20, and a hole 15 is opened at the layer 14 on a hole 11' for forming an emitter region of the transistor T
2 . The polycrystalline silicon layer 13 of lower layer is patterned to remove unnecessary part. It is then heat treated for approx. 12∼13min in dry O
2 at 1,000°C, thereby diffusing n type impurities P, As in the layer 13, and an emitter region E
1 is formed in the first base region B
1 , and an emitter region E
2 is formed in the second base region B
2 .
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过区分n型扩散区的磷和砷的密度比，形成在一个热扩散步骤中具有准确不同扩散深度的n型区域。构成：在形成有基板20的晶体管T1，T2的区域中分别形成n +型掩埋层A1，A2和n型岛状区域C1，C2。多晶硅13，其中P和As 规定的密度以P / As = 32的比例添加被覆盖在基板20的整个表面上。第二绝缘层14（例如氧化硅）被覆盖在基板20的整个表面上，并且孔15是在层11上开有用于形成晶体管T2的发射极区的孔11'。对下层的多晶硅层13进行图案化以除去不必要的部分。然后将其热处理约在干燥的O2中在1000℃下12-13分钟，从而扩散层13中的n型杂质P，As，并且在第一基区B1中形成发射区E1，并且在第二基中形成发射区E2 区域B2。

5. 发明专利

JP2006157029A Manufacturing system and method of semiconductor device 有权
标题翻译：制造系统和半导体器件的方法
公开(公告)号：JP2006157029A
公开(公告)日：2006-06-15
申请号：JP2005351128
申请日：2005-12-05
申请人： Toshiba Corp , 株式会社東芝
发明人： USHIKU YUKIHIRO , OGAWA AKIRA , KAKINUMA HIDENORI , SHUDO SHUNJI , ABE MASAYASU , AKIYAMA TATSUO , KOMATSU SHIGERU
IPC分类号： H01L21/02 , C23C16/52 , H01L21/00 , H01L21/3065 , H01L21/31 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing system of a semiconductor device which properly manages a maintenance interval of the individual processing apparatus, extends an operating time of each processing apparatus, reducing a wafer inspection process performed at the stage of completing each semiconductor manufacturing process, and shortens a manufacturing process period of a semiconductor device. SOLUTION: This system is provided with a processor 14 for executing process treatment using a semiconductor substrate 17, a self-diagonostic system 11a for receiving device information from the processor 14 and calculating an estimated quality value of the process treatment, an inspection device 19 for inspecting the result of the process treatment, and a computer 11. The computer 11 compares an inspection result and an estimated quality value, and maintains a parameter of the self-diagonostic system when the estimated quality value is valid and changes a parameter of the self-diagonostic system when the estimated quality value is invalid. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供适当地管理各个处理装置的维护间隔的半导体装置的制造系统，延长每个处理装置的操作时间，减少在完成每个处理装置的阶段执行的晶片检查处理半导体制造工艺，缩短半导体器件的制造工艺周期。解决方案：该系统设置有用于执行使用半导体衬底17的处理处理的处理器14，用于从处理器14接收设备信息并计算处理处理的估计质量值的自我对角线系统11a，检查用于检查处理结果的装置19和计算机11.计算机11将检查结果与估计的质量值进行比较，并且当估计的质量值有效时维持自我对角系统的参数，并且改变参数的估计质量值无效的自我对角线系统。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005109437A Manufacturing system and method of semiconductor device 有权
标题翻译：制造系统和半导体器件的方法
公开(公告)号：JP2005109437A
公开(公告)日：2005-04-21
申请号：JP2004189971
申请日：2004-06-28
申请人： Toshiba Corp , 株式会社東芝
发明人： USHIKU YUKIHIRO , OGAWA AKIRA , KAKINUMA HIDENORI , SHUDO SHUNJI , ABE MASAYASU , AKIYAMA TATSUO , KOMATSU SHIGERU
IPC分类号： H01L21/3065 , G05B19/418 , H01L21/00 , H01L21/02 , H01L21/31 , H01L21/316 , H01L21/331
CPC分类号： G05B19/4184 , G05B19/41885 , G05B2219/32368 , G05B2219/45031 , Y02P90/14 , Y02P90/22 , Y02P90/26 , Y02P90/265
摘要： PROBLEM TO BE SOLVED: To properly manage a maintenance interval of a processor and to shorten a manufacturing process period of a semiconductor device. SOLUTION: This system is provided with a processor 14 for executing process treatment using a semiconductor substrate 17, a self-diagonostic system 11a for receiving device information from the processor 14 and performing self-management of the processor 14, an inspection device 19 for inspecting the result of the process treatment, and a computer 11. The computer 11 judges whether or not to automatically restore the processor 14 based on the inspection result, and maintains a parameter of the self-diagonostic system 11a when the judgement result is valid and changes a parameter of the self-diagonostic system 11a when the judgement result is invalid. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：适当地管理处理器的维护间隔并缩短半导体器件的制造工艺周期。解决方案：该系统设置有用于执行使用半导体衬底17的处理处理的处理器14，用于从处理器14接收设备信息并执行处理器14的自我管理的自我对角线系统11a，检查设备 19，用于检查处理结果的结果以及计算机11.计算机11基于检查结果判断是否自动恢复处理器14，并且当判断结果为...时，维持自身对角线系统11a的参数当判断结果无效时有效并改变自身对角线系统11a的参数。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JPH03156979A BIPOLAR DIODE 失效
公开(公告)号：JPH03156979A
公开(公告)日：1991-07-04
申请号：JP29672789
申请日：1989-11-15
申请人： TOSHIBA CORP
发明人： MISHIO KOUICHI , TAKAHASHI SATOSHI , KOMATSU SHIGERU
IPC分类号： H01L29/866
摘要： PURPOSE:To prevent the increase in the internal resistance of base regions by providing a doped region of a maximum concentration at a distance from the surface of a semiconductor substrate in a processing step other than that for forming a shallow junction base. CONSTITUTION:A silicon semiconductor substrate includes an N-type epitaxial layer 30 in which P-type isolation region 31 is formed to define islands. Each island, including an NPN transistor 32 or a Zener diode 33, has an N-type buried layer 35. The individual islands are coated with insulator 34 composed of silicon nitride and silicon oxide. The insulator 34 has holes 36, through which emitter regions 37 and inner and outer base regions 38 and 39 are formed. A conductive metal layer 40 is deposited over the holes. The N-type buried layer 35 is connected with a deep-N region to provide a collector contact. This structure prevents the internal resistance of the base region from increasing.

8. 发明专利

JPS61156850A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS61156850A
公开(公告)日：1986-07-16
申请号：JP27618684
申请日：1984-12-28
申请人： TOSHIBA CORP
发明人： KOMATSU SHIGERU
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To obtain the titled device of large capacitance per unit area by the availability of a thin capacitor insulation film by a method wherein a conductive protection film having acid-resistance is interposed between the capacitor insulation film and the upper electrode. CONSTITUTION:A field oxide film 12 is formed on the surface of an Si substrate 11. Next, the lower electrode 13 having high-temperature heat-resistance and the property of being oxidized is formed. Successively, after deposition of a CVD oxide film 14 over the whole surface, an aperture 15 is provided above the lower electrode 13, and an Si nitride film 16 serving as the capacitor insulation film is deposited. Then, a polycrystalline Si pattern 17 is formed. This Si pattern 17 is acid-resistant to hydrofluoric acid and the like and serves as the protection film for the Si nitride film 16. The surface of the Si pattern 17 is oxidized with hydrofluoric acid or the like and cleaned; then, the upper electrode 18 is formed. Since this capacitor does not have the Si nitride film 16 corroded by hydrofluoric acid or the like during oxidation, the capacitance per unit are can be increased by thinning the Si nitride film 16.

9. 发明专利

JPS6113656A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS6113656A
公开(公告)日：1986-01-21
申请号：JP13378884
申请日：1984-06-28
申请人： Toshiba Corp
发明人： KOMATSU SHIGERU , KIHARA KAZUO
IPC分类号： H01L21/822 , H01L27/04
CPC分类号： H01L27/04
摘要： PURPOSE:To manufacture a capacitor without damaging other elements when using an insulating film having high permittivity by forming an insulating film shaping the capacitor and an insulating film protecting said insulating film forming the capacitor before shaping other elements. CONSTITUTION:An N type buried layer 22, an N type epitaxial layer 23 and a P type element isolation region 24 are formed to the surface of a P type Si substrate 21, and an N type collector contact region 25 and an N type diffusion layer 26 are shaped. A field insulating film 27 is formed. The film 27 is etched selectively to form thermal oxide films 28. The film 28 on a capacitor forming region is removed selectively, and an Si nitride film 29 constituting a capacitor and an oxide film 30 for protecting the film 29 are shaped. A P type base region 31 is formed. An Si nitride film 32 is deposited, and one part of the film 28 and the film 30 are exposed. An N type emitter region 33 is shaped, and an emitter electrode 34, a base electrode 35, a collector electrode 36, an electrode 37 for the capacitor and a leading-out electrode 38 for the capacitor are formed.
摘要翻译：目的：在使用具有高介电常数的绝缘膜时，通过形成电容器的绝缘膜和在形成其它元件之前形成电容器的绝缘膜来保护绝缘膜，制造电容器而不损坏其它元件。构成：在P型Si衬底21的表面上形成N +型掩埋层22，N型外延层23和P +型元件隔离区24，并且N +型集电体接触区域25和N +型扩散层26成形。形成场绝缘膜27。选择性地蚀刻膜27以形成热氧化膜28.电容器形成区域上的膜28被选择性地去除，并且构成电容器的氮化硅膜29和用于保护膜29的氧化物膜30成形。形成P型基区31。沉积Si氮化物膜32，并且暴露出膜28和膜30的一部分。形成N +型发射极区33，形成发射电极34，基极35，集电极36，电容器用电极37和电容器用引出电极38。

10. 发明专利

JPS57117268A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS57117268A
公开(公告)日：1982-07-21
申请号：JP432781
申请日：1981-01-14
申请人： Toshiba Corp
发明人： KOMATSU SHIGERU , NAKAMURA MICHIO , FUJITA KATSUJI
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L23/522 , H01L23/58 , H01L27/08
CPC分类号： H01L23/585 , H01L23/522 , H01L27/0802 , H01L2924/0002 , Y10S73/04 , Y10S257/925 , H01L2924/00
摘要： PURPOSE: To prevent variation of paired characteristic of a semiconductor device by a method wherein the ratio of crossing area of wiring layers to be formed by crossing on plural diffusion resistors being necessitated with paired characteristic mutually is equalized with the ratio of resistances of the diffusion resistors.
CONSTITUTION: Diffusion resistors 12
1 , 12
2 to be necessitated with paired characteristic are formed on a silicon substrate 11. Wirings 14
1 , 14
1 ', 14
2 , 14
2 ' are formed at both the ends of the resistors 12
1 , 12
2 . A wiring 16 to connect between another element is arranged crossing only with the one side diffusion resistor 12
1 . A dummy wiring 17 has the equal crossing area with the crossing area of the wiring 16 and the resistor 12
1 ' and is made to generate the equal piezoelectric resistance effect in the resistor 12
2 .
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：为了防止半导体器件的配对特性的变化，其中通过使成对特征相互需要的多个扩散电阻器上交叉形成的布线层的交叉面积的比与扩散电阻器的电阻的比值相等的方法。构成：在硅衬底11上形成必要具有成对特性的扩散电阻器121,122。在电阻器121,122的两端形成有布线141,141'，142,142'。布线16 另一个元件布置为仅与单侧扩散电阻器121交叉。虚拟布线17具有与布线16和电阻器121'的交叉区域相等的交叉面积，并且使得在电阻器122中产生相等的压电电阻效应。

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