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1. 发明专利

JP2012204668A Plasma etching method and storage medium 有权
标题翻译：等离子体蚀刻方法和储存介质
公开(公告)号：JP2012204668A
公开(公告)日：2012-10-22
申请号：JP2011068694
申请日：2011-03-25
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： IGARASHI YOSHIKI , NARUSHIGE KAZUKI
IPC分类号： H01L21/3065
CPC分类号： H01L21/31122 , H01J37/32082 , H01L21/31144
摘要： PROBLEM TO BE SOLVED: To provide a plasma etching method capable of etching an organic film without causing defects in an etching shape such as bowing when etching the organic film by using an inorganic film as a mask.SOLUTION: The plasma etching method comprises: using a plasma etching apparatus which has an upper electrode having a surface made of a silicon-containing material and a lower electrode on which a substrate to be treated is mounted, which are arranged in a treatment container, and generates plasma between the upper electrode and the lower electrode to etch the substrate to be treated with plasma; and etching the organic film of the substrate to be treated with plasma by using the inorganic film as the mask. The method further comprises: etching the organic film halfway with plasma; then applying a negative direct voltage to the upper electrode while generating plasma, to form a protection film containing the silicon-containing material of the upper electrode, at a side wall of an etched portion; and then continuing the plasma etching.
摘要翻译：要解决的问题：提供一种能够通过使用无机膜作为掩模蚀刻有机膜时，能够蚀刻有机膜而不引起蚀刻形状如弯曲等缺陷的等离子体蚀刻方法。解决方案：等离子体蚀刻方法包括：使用等离子体蚀刻装置，其具有上部电极，其具有由含硅材料制成的表面和安装有待处理的基板的下部电极，其布置在处理容器，并在上电极和下电极之间产生等离子体，以用等离子体蚀刻待处理的衬底; 并通过使用无机膜作为掩模来蚀刻待处理的基板的有机膜。该方法还包括：用等离子体中途刻蚀有机膜; 然后在产生等离子体的同时向上电极施加负直流电压，以在蚀刻部分的侧壁处形成含有上电极的含硅材料的保护膜; 然后继续等离子体蚀刻。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2007180358A Plasma etching method and computer-readable recording medium 有权
标题翻译：等离子体蚀刻方法和计算机可读记录介质
公开(公告)号：JP2007180358A
公开(公告)日：2007-07-12
申请号：JP2005378608
申请日：2005-12-28
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： SATO MANABU , IGARASHI YOSHIKI , KON YASUMITSU , HONDA MASANOBU
IPC分类号： H01L21/3065
CPC分类号： H01L21/0273 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： PROBLEM TO BE SOLVED: To provide a plasma etching method capable of etching an organic film or an amorphous carbon film on a substrate to be treated at a high etching rate and at a high selection rate, when the organic film or the amorphous carbon film is etched by using a mask containing silicon. SOLUTION: A first high-frequency power having a relatively higher frequency from a first high-frequency power supply 89, and a second high-frequency power having a relatively lower frequency from a second high-frequency power supply 90, are applied to a lower electrode 16 for supporting a wafer in a chamber 10. A DC voltage from a variable DC power supply 50 is applied to an upper electrode 34 oppositely arranged to the lower electrode 16, and the inside of the chamber 10 is supplied with a treating gas containing no CF gas to generate plasma. The organic film or the amorphous carbon film on the substrate to be treated is plasma-etched by using the mask containing silicon. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供能够以高蚀刻速率和高选择速度蚀刻待处理基板上的有机膜或无定形碳膜的等离子体蚀刻方法，当有机膜或非晶态通过使用含有硅的掩模来蚀刻碳膜。解决方案：应用具有来自第一高频电源89的相对较高频率的第一高频功率和来自第二高频电源90的具有相对较低频率的第二高频功率到用于将晶片支撑在室10中的下电极16.来自可变直流电源50的直流电压被施加到与下电极16相对布置的上电极34，并且向腔10的内部供应有处理不含CF气体的气体来产生等离子体。通过使用含有硅的掩模，对待处理的基板上的有机膜或无定形碳膜进行等离子体蚀刻。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2005101289A Plasma ashing method 有权
标题翻译：等离子喷雾方法
公开(公告)号：JP2005101289A
公开(公告)日：2005-04-14
申请号：JP2003333315
申请日：2003-09-25
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： KUBOTA KAZUHIRO , IGARASHI YOSHIKI , TAWARA SHIGERU , OKAMOTO SUSUMU , SHINDO TOSHIHIKO , OYA YOSHINOBU
IPC分类号： G03F7/42 , H01L21/027 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/311 , H01L21/461
CPC分类号： H01L21/31116 , H01J2237/3342 , H01L21/31138
摘要： PROBLEM TO BE SOLVED: To remove a resist film on a workpiece by ashing without giving any damage onto the low-k film of the workpiece. SOLUTION: A Low-k film is deteriorated by O radicals producing in a chamber 102 and the dielectric constant (k value) of the Low-k film increases as a result. A pressure within the chamber 102 is reduced and a mixed gas of an O 2 gas and an inert gas (especially Ar gas and N 2 gas) is used as a processing gas, resulting in reducing the density of the O radicals within the chamber. As a result, the film quality of the Low-k film can be kept appropriate in a plasma ashing step. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过灰化去除工件上的抗蚀剂膜，而不会对工件的低k膜造成任何损坏。解决方案：低k膜由于在室102中产生的O自由基而劣化，并且Low-k膜的介电常数（k值）因此而增加。室102内的压力降低，并且使用O气体和惰性气体（特别是Ar气体和N 2 气体）的混合气体作为处理气体，导致室内O自由基的密度降低。结果，Low-k膜的膜质量可以在等离子体灰化步骤中保持适当。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2008078515A Plasma treatment method 审中-公开
标题翻译：等离子体处理方法
公开(公告)号：JP2008078515A
公开(公告)日：2008-04-03
申请号：JP2006258177
申请日：2006-09-25
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： HONDA MASANOBU , SATO MANABU , IGARASHI YOSHIKI
IPC分类号： H01L21/3065
CPC分类号： H01L21/467 , H01J37/32091 , H01J37/32165 , H01L21/31116
摘要： PROBLEM TO BE SOLVED: To provide a plasma treatment method by which both a high etching rate and a high etching selection ratio to a grounding layer can be obtained when a layer to be etched including a Si-containing film is etched by using silicon, a silicon nitride film, a silicon carbide film, a charcoal silicon nitride film or the like as the grounding layer. SOLUTION: While installing a substrate to be treated, there is used a plasma treatment device equipped with: a primary electrode to which a first high frequency power supply is connected; and a secondary electrode provided in opposition to the primary electrode. In regard to the substrate to be treated comprising at least: a resist layer in which a pattern is formed; the layer to be etched including the Si-containing film of a lower layer; and further the grounding layer of the lower layer, the layer to be etched is etched, while applying a negative dc voltage whose absolute value is 100 V or higher, 1,500 V or lower or high frequency power lower than 4 MHz to the secondary electrode. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种等离子体处理方法，其中当通过使用含有Si的膜蚀刻包括含Si膜的层时，可以获得对接地层的高蚀刻速率和高蚀刻选择比硅，氮化硅膜，碳化硅膜，碳氮化硅膜等作为接地层。解决方案：在安装待处理的基板时，使用等离子体处理装置，其配备有连接有第一高频电源的主电极; 以及与主电极相对设置的次级电极。关于待处理的基材，至少包括：形成图案的抗蚀剂层; 待蚀刻的层包括下层的含Si膜; 并且进一步对下层的接地层进行蚀刻，同时将绝对值为100V或更高，1500V或更低或低于4MHz的高频功率的负直流电压施加到次级电极。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2011216817A Method for forming mask pattern, and method for manufacturing semiconductor device 有权
标题翻译：用于形成掩模图案的方法，以及制造半导体器件的方法
公开(公告)号：JP2011216817A
公开(公告)日：2011-10-27
申请号：JP2010085956
申请日：2010-04-02
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： YAEGASHI HIDETAMI , IGARASHI YOSHIKI , NARUSHIGE KAZUKI , TAKEKAWA TAKAHITO
IPC分类号： H01L21/027 , H01L21/3065
CPC分类号： H01L21/31138 , H01J37/32091 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/31116 , H01L21/32139
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a mask pattern and a method for manufacturing a semiconductor device, in which a fine mask pattern can be formed by an SWP technique, while preventing a core member made of a resist film from being deformed when a silicon oxide film is formed and etched back.SOLUTION: The disclosed method includes a first pattern formation step S13, wherein a pattern including a second line section is formed by etching an antireflection film with a first line section as a mask, the first line section being formed from a photoresist film; an irradiation step S14 wherein the photoresist film is irradiated with electrons; a silicon oxide film formation step S15 wherein a silicon oxide film is formed; an etching back step S16, wherein the silicon oxide film is etched back so as to be left as side wall sections of the second line section, and a second pattern formation step S18, wherein a mask pattern formed from the silicon oxide film and including a third line section left as the sidewall section thereof, is formed by ashing the second line section.
摘要翻译：要解决的问题：提供一种形成掩模图案的方法和用于制造半导体器件的方法，其中可以通过SWP技术形成精细的掩模图案，同时防止由抗蚀剂膜制成的芯部件变形当形成氧化硅膜并回蚀刻时。本发明的方法包括第一图案形成步骤S13，其中通过用第一线段作为掩模蚀刻抗反射膜形成包括第二线段的图案，第一线段由光致抗蚀剂膜形成; 照射步骤S14，其中用电子照射光致抗蚀剂膜; 氧化硅膜形成步骤S15，其中形成氧化硅膜; 蚀刻返回步骤S16，其中氧化硅膜被回蚀刻成为第二线段的侧壁部分，第二图案形成步骤S18，其中由氧化硅膜形成的掩模图案包括通过灰化第二线路部分而形成作为其侧壁部分留下的第三线路段。

6. 发明专利

JP2005353698A Etching method 有权
标题翻译：蚀刻方法
公开(公告)号：JP2005353698A
公开(公告)日：2005-12-22
申请号：JP2004170361
申请日：2004-06-08
申请人： Tokyo Electron Ltd , 東京エレクトロン株式会社
发明人： IGARASHI YOSHIKI , NAITO WAKAKO
IPC分类号： H01L21/3065
摘要： PROBLEM TO BE SOLVED: To provide an etching method which can prevent a change in etching characteristics due to a memory effect while maintaining the merits of all-in-one etching.
SOLUTION: After a first etching process, there is a deposit 70 attaching to the internal wall surface of a chamber 2. After carrying out cleaning for the purpose of removing the deposit 70, a second etching process is conducted. The cleaning is carried out using a mixed gas of O
2 gas and N
2 gas as a cleaning gas under the zero bias condition wherein no bias voltage is applied to a wafer W, with the internal pressure of the chamber being 50-200 mTorr, an O
2 flow rate being 5-15 mL/min, and an N
2 flow rate being 100-400 mL/min.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以防止由于记忆效应而导致的蚀刻特性变化同时保持一体蚀刻优点的蚀刻方法。解决方案：在第一蚀刻工艺之后，存在附着到室2的内壁表面的沉积物70.为了去除沉积物70进行清洁，进行第二蚀刻工艺。在零偏压条件下，使用O SB 2气体和N 2 SB 2气体的混合气体作为清洁气体进行清洗，其中没有偏置电压施加到晶片W ，室内压为50-200mTorr，O 2 流量为5-15mL / min，N 2 流量为100- 400 mL / min。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2002100607A METHOD FOR ETCHING OXIDE FILM 失效
公开(公告)号：JP2002100607A
公开(公告)日：2002-04-05
申请号：JP2000287259
申请日：2000-09-21
申请人： TOKYO ELECTRON LTD
发明人： IGARASHI YOSHIKI , BAIDEIA NASAN BALASUBRAMANIAN , SUEMASA TOMOKI , INASAWA KOICHIRO
IPC分类号： H01L21/302 , C23F1/00 , H01J37/32 , H01L21/3065 , H01L21/311 , H01L21/461
摘要： PROBLEM TO BE SOLVED: To provide a method for etching an oxide film which can increase the selectivity of etching to a resist when dry-etching the oxide film. SOLUTION: A work piece W to be processed, on which the oxide film is formed, is positioned in a processing, chamber 1, which can hold the work piece in vacuum and plasma of etching gas is generated in the processing chamber 1. When etching the oxide film of the work piece W in the chamber, the etching gas contains gas C4F6 and gas O2, and the ratio C4F6/O2 of gas C4F6 to gas O2 is 1.0-1.5.

8. 发明专利

JP2002270586A ETCHING METHOD OF ORGANIC BASED INSULATING FILM AND DUAL DAMASCENE PROCESS 失效
公开(公告)号：JP2002270586A
公开(公告)日：2002-09-20
申请号：JP2001065459
申请日：2001-03-08
申请人： TOKYO ELECTRON LTD
发明人： IGARASHI YOSHIKI , SUEMASA TOMOKI , INASAWA KOICHIRO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To enhance selection rate of an SiOC based low permittivity film and a silicon nitride film while reducing a microtrench during etching. SOLUTION: In etching the SiOC based low permittivity film using a C4 F8 /Ar/ N2 based mixture gas, flow rate ratio of Ar is set at 80% or above.

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