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1. 发明专利

JP2004214662A Gettering of high dielectric constant gate dielectrics defect using dopant 审中-公开
标题翻译：使用DOPANT的高介电常数栅极电介质缺陷
公开(公告)号：JP2004214662A
公开(公告)日：2004-07-29
申请号：JP2003430016
申请日：2003-12-25
申请人： Texas Instruments Inc , テキサスインスツルメンツインコーポレイテッド
发明人： COLOMBO LUIGI , CHAMBERS JAMES J , ROTONDARO ANTONIO L P
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： PROBLEM TO BE SOLVED: To provide a method to perform gettering of defect in a high dielectric constant gate dielectrics .
SOLUTION: A transistor (400) is formed by performing a passivation process for an electrically active defect (408) at the top (406) of a high dielectric constant dielectric material layer (404). The high dielectric constant dielectric material layer is used to form high dielectric gate dielectrics in the transistor. A gate electrode layer (414) is formed on the high dielectric constant dielectric material layer and patterned. After that, a gate structure including a gate electrode and high dielectric constant gate dielectrics is formed. The electrically active defect is passivated using materials including dopant that is induced by the defect and neutralized. Therefore, the passivated defect does not obstruct the doping process of other transistors (such as the formation of source and drain regions) and does not have an adverse impact on the performance, reliability and yield of a semiconductor device to be obtained.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种在高介电常数栅极电介质中吸收缺陷的方法。解决方案：通过对高介电常数介电材料层（404）的顶部（406）处的电活性缺陷（408）执行钝化处理来形成晶体管（400）。高介电常数介电材料层用于在晶体管中形成高介电栅极电介质。在高介电常数电介质材料层上形成栅电极层（414）并进行图案化。之后，形成包括栅电极和高介电常数栅极电介质的栅极结构。使用由缺陷诱导并中和的掺杂剂的材料钝化电活性缺陷。因此，钝化缺陷不会妨碍其他晶体管的掺杂过程（例如形成源极和漏极区），并且不会对要获得的半导体器件的性能，可靠性和产量产生不利影响。版权所有（C）2004，JPO＆NCIPI

2. 发明专利

JP2004247736A Interface layer growth for high-k gate dielectric at high temperature 审中-公开
公开(公告)号：JP2004247736A
公开(公告)日：2004-09-02
申请号：JP2004034537
申请日：2004-02-12
申请人： Texas Instruments Inc , テキサスインスツルメンツインコーポレイテッド
发明人： COLOMBO LUIGI , CHAMBERS JAMES J , ROTONDARO ANTONIO L P , VISOKAY MARK R
IPC分类号： C23C28/00 , H01L21/02 , H01L21/28 , H01L21/316 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28185 , C23C28/00 , H01L21/02238 , H01L21/02255 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/31155 , H01L21/31662 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a high-quality, ultra-thin-film interface oxide layer 418 suitable for use as a high-permittivity gate insulating film 424 when manufacturing a semiconductor.
SOLUTION: An oxidizer atmosphere containing oxygen and a reducing agent is used at a high temperature for growing the interface oxide layer 418. In the method, the oxygen grows the oxide layer 418 and the reducing agent decreases the growth. A growth speed in the oxide layer 418 can be controlled by adjusting a partial pressure obtained by multiplying the ratio of the reducing agent in a gaseous phase by total pressure. When the growth speed of the oxide layer 418 is controlled for delaying, a layer having a thickness of approximately 10 angstroms or less can be easily formed. When the oxide layer 418 is grown at a high temperature, a layer having a favorable bonding state and high quality can be produced and a product having better performance and reliability is generated.
COPYRIGHT: (C)2004,JPO&NCIPI

3. 发明专利

JP2004111922A Gate dielectric and method therefor 审中-公开
公开(公告)号：JP2004111922A
公开(公告)日：2004-04-08
申请号：JP2003203606
申请日：2003-07-30
申请人： Texas Instruments Inc , テキサスインスツルメンツインコーポレイテッド
发明人： ROTONDARO ANTONIO L P , COLOMBO LUIGI , BEVAN MALCOLM J
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/823857
摘要： PROBLEM TO BE SOLVED: To simply manufacture a CMOS device having a gate dielectric made of a high-k dielectric.
SOLUTION: The CMOS gate dielectric made of the high-k metal silicates by passivating a silicon surface with nitrogen compound prior to high-k dielectric deposition is provided. Optionally, a silicon dioxide monolayer may be preserved at the interface.
COPYRIGHT: (C)2004,JPO

4. 发明专利

JPH1174488A INTEGRATED CIRCUIT CAPACITOR AND MEMORY 失效
公开(公告)号：JPH1174488A
公开(公告)日：1999-03-16
申请号：JP18447798
申请日：1998-06-30
申请人： TEXAS INSTRUMENTS INC
发明人： XING GUOQUIANG , SUMMERFELT SCOTT R , KHAMANKAR RAJESH , CERNY GLENN A , VISOKAY MARK R , COLOMBO LUIGI , KRESSLEY MARK A
IPC分类号： H01L27/108 , H01L21/02 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To strengthen bonding of capacitor bottom electrodes to interlayer insulators and to raise the conductivity of the bottom electrodes to conductive plugs by a method wherein the capacitor bottom electrodes of a memory circuit comprising a memory cell are bonded to the interlayer insulators making barrier body layers, the conductive plugs and the like interpose between the side surfaces of the interlayer insulators and making conductive bonding accelerating layers interpose between the bottom electrodes and the upper surfaces of the interlayer insulators. SOLUTION: Two capacitor bottom electrodes 204, which have a charge storage layer or a capacitor insulator 212 and a top electrode 214, of a memory circuit comprising a memory cell are bonded on a silicon substrate 200 via silicon dioxide interlayer insulators 202 and barrier body layers 208 consisting of a Ti-Al-N layer. The insulators 202 are separated from each other by the layers 208, silicide layers 207 consisting of a TiSi2 layer and conductive plugs 206, which are laminated. The electrodes 204 consist of a platinum layer of a thickness of about 350 nm or the like, are formed into a rectangular shape and conductive bonding accelerating layers 210 consisting of a Ti-N layer or the like are respectively interposed between the electrodes 204 and the insulators 202 under the lower surfaces of the electrodes 204. Thereby, a bonding of the electrodes 204 to the insulators 205 and the conductivity of the electrodes 204 to the plugs are enhanced.

5. 发明专利

JP2003218108A CVD DEPOSITION OF M-SiO GATE DIELECTRIC 审中-公开
公开(公告)号：JP2003218108A
公开(公告)日：2003-07-31
申请号：JP2002361573
申请日：2002-12-13
申请人： TEXAS INSTRUMENTS INC
发明人： COLOMBO LUIGI , VISOKAY MARK R , BEVAN MALCOLM J , ROTONDARO ANTONIO L P
IPC分类号： H01L21/318 , C23C16/30 , C23C16/56 , H01L21/28 , H01L21/316 , H01L29/51 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To form a highly dielectric gate dielectric having no boundary oxide. SOLUTION: An M-SiN or M-SiON CVD such as HfSiO 2 is used to form a highly dielectric gate dielectric film (106). Post-deposition annealing is used to adjust the concentration of nitrogen. COPYRIGHT: (C)2003,JPO

6. 发明专利

JP2001244426A MANUFACTURING METHOD OF FERROELECTRIC MEMORY CELL 失效
公开(公告)号：JP2001244426A
公开(公告)日：2001-09-07
申请号：JP2000389018
申请日：2000-12-21
申请人： TEXAS INSTRUMENTS INC
发明人： SUMMERFELT SCOTT R , THEODORE S MOYES , GUOJIAN SHIN , COLOMBO LUIGI , SAKODA TOMOYUKI , STEVEN R GILBERT , ALVIN LAUCKE , SHOOMIN MAA , RAHIM KABARI , MIRKARIMI LAURA WILLIS , AMANO JUN
IPC分类号： H01L21/316 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a ferroelectric capacitor positioned on a certain structure. SOLUTION: The manufacturing method of a ferroelectric memory cell includes a step for forming on a certain structure, i.e., a dielectric layer 112 having therein a conductive contact 114, a bottom portion electrode 124 having a top surface and a plurality of side surfaces; a step for forming on the bottom portion electrode 124, a capacitor dielectric 126 made of a ferroelectric material which has a top surface and a plurality of side surfaces; a step for forming on the capacitor dielectric 126 a top portion electrode 128, 130 having a top surface and a plurality of side surfaces, which makes a ferroelectric capacitor 125 have the bottom portion electrode 124, the capacitor dielectric 126, and the top portion electrode 128, 130; a step for forming barrier layers 118, 120 on the side surfaces of the bottom portion electrode 124, the capacitor dielectric 126, and the top portion electrode 128, 130; a step for forming on the barrier layers 118, 120 and on the structure 112, 114, a dielectric layer 134 having a top surface and a bottom surface; and a step for performing a heating step during a certain time in the atmosphere of a gas selected from the group comprising an argon gas, a nitrogen gas, and the combination of them at a temperature of 400-900 deg.C after performing the step for forming the barrier layers 118, 120.

7. 发明专利

JP2001210798A USE OF INSULATING AND CONDUCTIVE BARRIER FOR PROTECTING CAPACITOR STRUCTURE 失效
公开(公告)号：JP2001210798A
公开(公告)日：2001-08-03
申请号：JP2000389336
申请日：2000-12-21
申请人： TEXAS INSTRUMENTS INC
发明人： SUMMERFELT SCOTT R , STEVEN R GILBERT , COLOMBO LUIGI , THEODORE S MOYES
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a capacitor structure for a semiconductor device which does not degrade by hydrogen or contamination. SOLUTION: A capacitor structure (125 of figure 1) comprises a lower electrode (124 of Fig. 1) provided with a side surface and an upper front surface, a capacitor dielectric (126 of Fig. 1) which, comprising an upper front surface and a side surface, is provided on the upper front surface of the lower electrode having such electric characteristics as to degrade by hydrogen, provided with upper electrodes (128 and 130 of Fig. 1) which comprise an upper front surface and side surface and provided on the capacitor dielectrics, a silicon nitride layer (120 of Fig. 1) provided on the side surface of capacitor dielectrics, and an aluminum oxide layer (118 of Fig. 1) provided between the side surface of capacitor dielectrics and silicon nitride layer.

8. 发明专利

JP2000133633A ETCHING OF MATERIAL USING HARD MASK AND PLASMA ACTIVATING ETCHANT 失效
公开(公告)号：JP2000133633A
公开(公告)日：2000-05-12
申请号：JP25631699
申请日：1999-09-09
申请人： TEXAS INSTRUMENTS INC
发明人： MOISE THEODORE S , XING GUOQIANG , VISOKAY MARK , GAYNOR JUSTIN F , SUMMERFELT SCOTT R , GILBERT STEPHEN R , CELII FRANCIS , COLOMBO LUIGI , KRESSLEY MARK A
IPC分类号： H01L21/302 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/311 , H01L21/8242 , H01L21/8246 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To form a paraelectric capacitor and a ferroelectric capacitor uing a metallic oxide dielectric material, by a method wherein a material is etched using a hard mask formed of a nitride of a compound of titanium with aluminum, and a plasma activating etchant set at a temperature in a specified range and containing chlorine, oxygen and nitrogen. SOLUTION: Sidewall dielectric bodies 308 are formed on a silicon substrate 300 and the dielectric bodies 308 are covered with a planarized dielectric layer 314. Then, holes are demarcated in the layer 314, a material is etched to form bit lines 316 and a dielectric layer 318 is formed on the bit lines 316 and the remaining layer 314. Subsequently, an adhesion layer 324 consisting of titanium and aluminum layers is deposited on the layer 318, and a hard mask layer 328 consisting of titanium and aluminium layers is deposited on the layer 324 via a Pt layer 326. An ARC layer 329 is deposited on this layer 328 and the layer 328 and the ARC layer 329 are etched using a plasma activating etchant.

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