专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2007295132A Data generating apparatus 有权
标题翻译：数据发生装置
公开(公告)号：JP2007295132A
公开(公告)日：2007-11-08
申请号：JP2006118524
申请日：2006-04-21
申请人： Tektronix Japan Ltd , 日本テクトロニクス株式会社
发明人： MIKI YASUHIKO
IPC分类号： H03K3/78 , H03M9/00
CPC分类号： G11C7/16 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： PROBLEM TO BE SOLVED: To provide a technology of stabilizing a time from the arrival of a trigger signal to a substantial data output start. SOLUTION: In this data generating apparatus, a memory 54 supplies parallel data according to a frequency division clock D_CLK. An address counter 52 gives the same address to the memory 54 until the trigger signal arrives and advances addresses when the trigger signal arrives. A hexadecimal counter 62 counts a clock CLK faster than the frequency division clock and the count is circulated by each period of the frequency division clocks. A trigger information latch 64 latches the count of the counter 62 when receiving the trigger signal and gives the latched count to an MUX 58. The MUX 58 selectively generates parallel data in 16 bits from parallel data in total 32 bits received at first and second input terminals I 1 , I 2 according to the latch count. A parallel serial conversion circuit 60 converts rearranged parallel data from the MUX 58 into serial data according to the clock CLK. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种将从触发信号的到达到实质数据输出开始的时间稳定的技术。解决方案：在该数据生成装置中，存储器54根据分频时钟D_CLK提供并行数据。地址计数器52向存储器54提供相同的地址，直到触发信号到达并且当触发信号到达时提前地址。十六进制计数器62比时分钟时钟更快地对时钟CLK进行计数，并且计数被分频时钟的每个周期循环。触发信息锁存器64在接收到触发信号时锁存计数器62的计数，并将锁存的计数提供给MUX 58.MUX 58有选择地从并行数据产生16位并行数据，总共32位在第一和第二输入端端子I 1 ，I 2 。并行串行转换电路60根据时钟CLK将从MUX 58重新排列的并行数据转换为串行数据。版权所有（C）2008，JPO＆INPIT

IPRDB

热门服务

关于我们

友情链接

联系方式