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1. 发明专利

JP2006042078A Voltage controlled oscillator and frequency adjustment method therefor 审中-公开
标题翻译：电压控制振荡器及其频率调整方法
公开(公告)号：JP2006042078A
公开(公告)日：2006-02-09
申请号：JP2004220874
申请日：2004-07-28
申请人： Tdk Corp , Tdk株式会社
发明人： HIRASAWA MINORU , KUDO KAZUO , SUZUKI YOSHIHIRO , SUDO MASAKATSU , ENDO TAKESHI , KANEYUKI TOMOHIKO , MIURA MITSURU
IPC分类号： H03B5/18 , H01P7/08
摘要： PROBLEM TO BE SOLVED: To provide a voltage controlled oscillator which exhibits sufficiently large shielding effect, is free from penetration of laser beams or the like and is therefore highly reliable.
SOLUTION: A strip line resonator 9 is formed inside a substrate 1 having lamination structure. A frequency adjusting trimming electrode 19 is formed inside the substrate 1. A trimming groove 20 formed by a laser beam irradiation from the main face (surface or rear face) of the substrate 1 consists of a first step trimming groove 20A and a second step trimming groove 20B. The first step trimming groove 20A is formed so that the trimming start point 22A side is deeper. The second step trimming groove 20B is formed deeper than the first step trimming groove 20A up to depth penetrating the trimming groove 19. The second step trimming groove 20B is formed so as to be overlapped at least to a part of the first step trimming groove 20A except the deep part 25 formed on the trimming start point 22A side.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供具有足够大的屏蔽效果的压控振荡器，不受激光束等的穿透，因此高可靠性。解决方案：带状线谐振器9形成在具有层叠结构的基板1内。在基板1内部形成有调频修整电极19.由基板1的主面（表面或背面）通过激光照射形成的修整槽20由第一台阶修整槽20A和第二台阶修整槽20B。第一台阶修整槽20A形成为使得修整起点22A侧更深。第二阶梯修剪槽20B形成为比第一阶梯修剪槽20A更深，深入穿过修剪槽19.第二阶梯修剪槽20B形成为至少与第一阶梯修剪槽20A的一部分重叠除了形成在修整起点22A侧的深部25。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2011234195A Multi-communication module 有权
标题翻译：多通道模块
公开(公告)号：JP2011234195A
公开(公告)日：2011-11-17
申请号：JP2010103631
申请日：2010-04-28
申请人： Tdk Corp , Tdk株式会社
发明人： KANEYUKI TOMOHIKO , TSUDA SHINJI , HAYASHI HIRONAO , HIRAOKA KAZUYA , MIURA MITSURU
IPC分类号： H04B1/38 , H04B1/10 , H04B1/3822 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To acquire good communication characteristic by reducing mutual interference of a plurality of communication functions of a module, without adding a circuit or part.SOLUTION: A multi-communication module comprises: a multi-function IC which is mounted on a surface of a multilayer substrate and includes two or more communication function pats realizing particular kinds of communication functions; and one or more ground electrodes placed to one or more wiring layers, respectively, including at least one internal wiring layer among a surface wiring layer, an internal wiring layer, and a backside wiring layer of the multilayer substrate. The multi-communication module mounts the IC on the surface of the substrate and forms two or more arrangement regions where communication function parts are placed, by placing each of the two or more communication function parts of the IC on each arrangement region when the multilayer substrate is viewed from plain surface. One or more ground electrodes on a closer side to the substrate surface including a ground electrode placed on the top layer are divided so that they correspond to arrangement regions where communication function parts are placed when the multilayer substrate is viewed from plain surface.
摘要翻译：要解决的问题：为了通过减少模块的多个通信功能的相互干扰来获得良好的通信特性，而不增加电路或部分。解决方案：多通信模块包括：多功能IC，其安装在多层基板的表面上，并且包括实现特定种类的通信功能的两个或更多个通信功能板; 以及一个或多个接地电极，其分别设置在一个或多个布线层上，包括在多层基板的表面布线层，内部布线层和背面布线层中的至少一个内部布线层。多通信模块通过将IC的两个或多个通信功能部件中的每一个放置在每个布置区域上而将多个基板的表面上的IC安装在基板的表面上并形成两个或更多个配置通信功能部件的布置区域，从平原表面看。将包括放置在顶层上的接地电极的基板表面的更靠近侧的一个或多个接地电极分开，使得它们对应于当从平坦表面观察多层基板时放置通信功能部件的布置区域。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2006066694A Property adjustment method and property adjustment device for multi-layer electronic components 审中-公开
标题翻译：多层电子元件的物业调整方法及物业调整装置
公开(公告)号：JP2006066694A
公开(公告)日：2006-03-09
申请号：JP2004248238
申请日：2004-08-27
申请人： Tdk Corp , Tdk株式会社
发明人： KUDO KAZUO , HIRASAWA MINORU , KANEYUKI TOMOHIKO , MIURA MITSURU
IPC分类号： H05K1/16 , B23K26/00 , B23K101/42 , H03B5/02 , H03B5/18 , H05K3/46
CPC分类号： H05K1/16 , H05K1/162 , H05K1/165 , H05K3/0008 , H05K3/0052 , H05K3/4611 , H05K2201/09918 , H05K2203/107 , H05K2203/171
摘要： PROBLEM TO BE SOLVED: To provide a property adjustment method and a property adjustment device for multi-layer electronic components that can efficiently adjust properties of multiple multi-layer electronic components on a set substrate. SOLUTION: This measurement method for multi-layer electronic components comprises a measurement process S21 for measuring the properties of multi-layer electronic components, a calculation process S22 for calculating the required amount of trimming based on the measurement result obtained in the measurement process S21, and a trimming process S23 for trimming a trimming pattern formed in the multi-layer electronic component according to the amount of trimming determined in the calculation process S22. By this, the trimming process S23 for a multi-layer electronic component already passing the measurement process S21 and the measurement process S21 for the other multi-layer electronic component can be performed concurrently. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以有效地调整设置基板上的多个多层电子部件的性能的多层电子部件的特性调整方法和特性调整装置。＆lt; P＆gt;解决方案：该多层电子部件的测定方法包括：测定多层电子部件的特性的测定工序S21，根据测定得到的测定结果计算所需的修整量的计算处理S22 处理S21和修整处理S23，用于根据在计算处理S22中确定的修整量来修整形成在多层电子部件中的修整图案。由此，可以同时进行已经通过测量处理S21的多层电子部件的修整处理S23和用于其他多层电子部件的测量处理S21。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2006033533A Voltage-controlled oscillator and frequency adjusting method thereof 审中-公开
标题翻译：电压控制振荡器及其频率调节方法
公开(公告)号：JP2006033533A
公开(公告)日：2006-02-02
申请号：JP2004210809
申请日：2004-07-16
申请人： Tdk Corp , Tdk株式会社
发明人： KANEYUKI TOMOHIKO , HIRASAWA MINORU , KUDO KAZUO
IPC分类号： H03B5/18 , H01P7/08
摘要： PROBLEM TO BE SOLVED: To provide a voltage-controlled oscillator which can be made small-sized and can obtain ample shielding effect and sufficient reliability, and to provide a frequency adjusting method thereof.
SOLUTION: A strip line resonator 9 is formed in a substrate 1 in laminated structure, and an electronic component 7 is mounted on the top surface of the substrate 1. A trimming electrode 19 for frequency adjustment is provided in the substrate 1. A region 22 on the top surface of the substrate 1, which corresponds to the trimming electrode 19, is regarded as a trimming region which is trimmed in a groove shape from the top surface to the trimming electrode 19 and where the electronic component is not mounted. The top surface is irradiated by a laser, and then the trimming electrode 19 is trimmed to adjust the frequency. Consequently, damages to the electronic component 7 and a conductor in the case that the reverse surface is irradiated by the laser are avoided. Further, neither a trimmer component nor the trimming electrode is provided on the top surface, so that the voltage-controlled oscillator can be made small-sized. Further, even if a laser light penetrates the substrate 1, this can be confirmed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以制成小尺寸的压控振荡器，并且可以获得足够的屏蔽效果和足够的可靠性，并提供其频率调节方法。解决方案：在层叠结构的基板1中形成带状线谐振器9，并且将电子部件7安装在基板1的上表面上。在基板1中设置有用于频率调节的修整电极19。基板1的与修整电极19对应的顶面的区域22被认为是从上表面到修整电极19被修整成槽状的修整区域，电子部件未安装。顶表面被激光照射，然后修整修整电极19以调节频率。因此，避免了在反面被激光照射的情况下对电子部件7和导体的损坏。此外，在顶面上既没有设置微调部件和修整电极，也可以使压控振荡器小型化。此外，即使激光穿过基板1，也可以确认。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2009239041A High frequency module and method of manufacturing same 有权
标题翻译：高频模块及其制造方法
公开(公告)号：JP2009239041A
公开(公告)日：2009-10-15
申请号：JP2008083555
申请日：2008-03-27
申请人： Tdk Corp , Tdk株式会社
发明人： ITAKURA MASAMI , HATTORI AKIRA , HIRAOKA KAZUYA , KANEYUKI TOMOHIKO , MIURA MITSURU
IPC分类号： H01L23/12 , H01L23/13 , H01L23/28
CPC分类号： H01L2224/48227 , H01L2924/19105
摘要： PROBLEM TO BE SOLVED: To provide a high frequency module that prevents a sealing resin from peeling owing to a thermal shock.
SOLUTION: The high frequency module 10 includes a wiring board 11, various electronic components 12 mounted on a principal surface (upper surface) of the wiring board 11 and including an IC chip, and a sealing resin 13 provided on the wiring board 11 to cover the electronic components 12. On the upper surface of the wiring board 11, a rough surface portion 14 is provided in a region of constant width along an outer periphery of the wiring board 11. The rough surface portion 14 is a region with a rougher surface than other regions on the principal surface 11a of the wiring board 11, and serves to enhance contact with the sealing resin 13. A recess is formed in the region where the rough surface portion 14 should be formed on the principal surface of the wiring board 11. Consequently, a surface of the rough surface portion 14 is slightly uneven in conformity with the uneven surface of the region where the rough surface portion 14 should be formed, thereby enhancing the contact with the sealing resin 13 more.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供防止密封树脂由于热冲击而剥离的高频模块。解决方案：高频模块10包括布线板11，安装在布线板11的主表面（上表面）上并且包括IC芯片的各种电子部件12以及设置在布线板上的密封树脂13 覆盖电子部件12.在布线基板11的上表面上，沿着布线基板11的外周，在宽度恒定的区域设置有粗糙面部14。粗糙面部14是具有比布线基板11的主面11a上的其它区域更粗糙的表面，并且增强与密封树脂13的接触。在形成有粗糙面部14的区域中形成有凹部，因此，粗糙表面部分14的表面与形成粗糙表面部分14的区域的不平坦表面一致，稍微不均匀，从而增强了与第 e密封树脂13更多。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2006032817A Assembly substrate for multilayer electronic component, and manufacturing method for multilayer electronic component 审中-公开
标题翻译：用于多层电子元件的组装基板和多层电子元件的制造方法
公开(公告)号：JP2006032817A
公开(公告)日：2006-02-02
申请号：JP2004212496
申请日：2004-07-21
申请人： Tdk Corp , Tdk株式会社
发明人： KUDO KAZUO , HIRASAWA MINORU , SUZUKI YOSHIHIRO , KANEYUKI TOMOHIKO , ENDO TAKESHI
IPC分类号： H05K1/16 , H03B5/02
CPC分类号： H01L23/544 , H01L21/4857 , H01L23/49822 , H01L24/97 , H01L2223/5442 , H01L2223/54473 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , H05K1/0269 , H05K1/16 , H05K3/0008 , H05K3/0052 , H05K2201/09781 , H05K2201/09918 , H05K2203/107 , H05K2203/171
摘要： PROBLEM TO BE SOLVED: To provide an assembly substrate for multilayer electronic components whereby trimming positions can be specified simply and accurately.
SOLUTION: The assembly substrate for the multilayer electronic components is the one from which a plurality of multilayer electronic components can be derived by cutting it. There are provided a trimming pattern 122b, formed on a predetermined insulating layer of a plurality of insulating layers and recognizing marks 122a formed on the same insulating layer as the trimming pattern 122b and for indicating the relative positional relations to the trimming pattern 122b. Thereby, even when a trimming position is specified by an image recognition, the specification of the trimming position can be performed by a very simple processing. In addition to this, since the recognition marks are formed on the same insulating layer as the trimming pattern, interlayer pattern discrepancies, etc. are not generated so as to be able to accurately specify the trimming position.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于多层电子部件的组装衬底，由此可以简单且准确地指定修剪位置。解决方案：用于多层电子部件的组装基板是通过切割多个电子部件可以导出多个多层电子部件的组装基板。提供了形成在多个绝缘层的预定绝缘层上的修整图案122b和形成在与修剪图案122b相同的绝缘层上的识别标记122a，并且用于指示与修剪图案122b的相对位置关系。因此，即使通过图像识别来指定修剪位置，也可以通过非常简单的处理来进行修整位置的指定。此外，由于识别标记形成在与修剪图案相同的绝缘层上，所以不能产生层间图案差异等，以便能够准确地指定修剪位置。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2005109187A Flip chip packaging circuit board and its manufacturing method, and integrated circuit device 审中-公开
标题翻译：卷芯片包装电路板及其制造方法和集成电路设备
公开(公告)号：JP2005109187A
公开(公告)日：2005-04-21
申请号：JP2003341309
申请日：2003-09-30
申请人： Tdk Corp , Tdk株式会社
发明人： KANEYUKI TOMOHIKO
IPC分类号： H01L21/60 , H01L21/56 , H01L23/12 , H01L23/498 , H01R13/52 , H05K1/18 , H05K3/34 , H05K5/00
CPC分类号： H05K3/3452 , H01L21/563 , H01L23/49816 , H01L23/49894 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/16225 , H01L2224/16237 , H01L2224/16238 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2924/01078 , H01L2924/01079 , H01R12/52 , H01R13/5216 , H05K2201/0989 , H05K2201/10674 , H05K2201/10977 , H01L2924/00 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a flip chip packaging circuit board capable of preventing a short circuit between adjacent bumps and realizing a satisfactory contact between the bumps and electrodes of the element at the time of the packaging, and its manufacturing method, and to provide an integrated circuit device. SOLUTION: Solder resists 16 are provided between adjacent bumps 22. The solder resists 16 are formed away from the bumps 22 at the predetermined distance, and openings 16a surrounding away the bumps 22 are patterned in the solder resist 16. A distance between the bumps 22 and the solder resists 16 is set on the basis of a mask overlay accuracy of the patterning. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种能够防止相邻凸点之间的短路并且在包装时实现元件的凸块和电极之间令人满意的接触的倒装芯片封装电路板及其制造方法，并提供集成电路装置。解决方案：在相邻的凸块22之间设置有抗蚀剂16.阻焊层16以预定的距离远离凸块22形成，并且在焊料抗蚀剂16上图形化围绕着凸块22的开口16a。基于图案化的掩模覆盖精度来设定凸块22和阻焊剂16。版权所有（C）2005，JPO＆NCIPI

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