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1. 发明专利

JPH0916398A INFORMATION PROCESSOR 失效
公开(公告)号：JPH0916398A
公开(公告)日：1997-01-17
申请号：JP16367695
申请日：1995-06-29
申请人： TOSHIBA MICRO ELECTRONICS , TOSHIBA CORP
发明人： FUJIMURA HIRONORI , TAKAI HIROYUKI , ONAINO SEIJI , TAKASUGI MIKIO , YAGUCHI TOSHIYUKI , KUNIMATSU ATSUSHI
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/34 , G06F9/38
摘要： PURPOSE: To provide an information processor by which plural pieces of data can be read/written by suppressing the capacity of hardware as much as possible and generating the address of plural pieces of data. CONSTITUTION: An instruction code inputted by an instruction input part 103 is decoded by an instruction decode part 105 and an operand and a control signal are generated. Corresponding to the control signal, an instruction division control part 109 outputs a division control signal and corresponding to the division control signal, an operand selecting part 107 outputs the operand inputted from the instruction decode part 105 with prescribed bit width. An arithmetic part 111 performs arithmetic by dividing the operand into the prescribed bit width corresponding to the division control signal, the calculated address is inputted, this address and the division control signal are outputted, and a memory access control part outputs data obtained from a memory to an arithmetic result holding part 113.

2. 发明专利

JP2001243069A DEVICE AND METHOD FOR PREDICTING BRANCH 失效
公开(公告)号：JP2001243069A
公开(公告)日：2001-09-07
申请号：JP2000056959
申请日：2000-03-02
申请人： TOSHIBA CORP
发明人： ONAINO SEIJI
IPC分类号： G06F9/32 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To improve branch predicting efficiency, and to shorten the executing time of an instruction by operating branch prediction by always using the latest branch predicting state. SOLUTION: The transition of a branch predicting state according to a branch instruction by-passes to the branch predicting state of the same branch instruction on a pipe like by a branch predicting state by-pass control device 21. Thus, the branch predicting state to be used for branch prediction and the transition of the branch predicting state can be always updated to the latest state.

3. 发明专利

JP2002189592A BRANCH PREDICTION DEVICE AND MICROPROCESSOR 失效
公开(公告)号：JP2002189592A
公开(公告)日：2002-07-05
申请号：JP2000390322
申请日：2000-12-22
申请人： TOSHIBA CORP
发明人： ONAINO SEIJI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide a branch prediction device for quickly determining whether or not the prediction of a branch target address is correct and preventing the decline of the processing efficiency of a program. SOLUTION: The branch prediction device 10 is provided with a branch instruction address holding device 21, a first comparator 22, a source register number storage device 23, an instruction kind storage device 24, an effective flag storage device 25, a branch address storage device 26, a second comparator 27, a branch target address storage device 28 and an entry controller 29. Since whether or not the prediction of the branch target address is correct is determined on the basis of the result of comparing the source register number of a register indirect branch instruction with the target register number of an instruction being executed at present, whether or not the predicted result of the branch target address is correct is determined without performing address calculation.

4. 发明专利

JPH07114498A MICROPROCESSOR 失效
公开(公告)号：JPH07114498A
公开(公告)日：1995-05-02
申请号：JP25846693
申请日：1993-10-15
申请人： TOSHIBA CORP
发明人： ONAINO SEIJI , YAGUCHI TOSHIYUKI , HISAMA YURIKO
IPC分类号： G06F12/06 , G06F9/30 , G06F9/312 , G06F9/46
摘要： PURPOSE:To provide a microprocessor in which the execution waiting tame of a following instruction accompanying the switching of a bank can be reduced. CONSTITUTION:This microprocessor is constituted of register banks FR1-FR4, a current bank pointer CBP which holds the position information of the saving area or that of the restoring area of the contents of the register banks, and a bank size designation register BS which designates the bank size in saving/ restoration. When the current bank pointer is designated as the destination operand of a prescribed instruction, the bank size designated by the bank size destination register BS is saved to a built-in RAM based on the content cbp of the current bank pointer at designated time, and the content of the current bank point is rewritten based on the intruction, and the information of bank size is restored from the built-in RAM to the bank register based on the content cbp' of the current bank pointer after rewrite.

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