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1. 发明专利

JPH01130397A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01130397A
公开(公告)日：1989-05-23
申请号：JP28768087
申请日：1987-11-14
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , KATO HIDEO , KANAZAWA KAZUHISA , SATO ISAO , KUMAGAI SHIGERU , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To improve the stability of operation and to increase a write margin by preventing a leak current from an output line at the time of rise of the potential of the output line. CONSTITUTION:D type transistors T207-T209 are connected in series for the purpose of outputting a boosting voltage to a column decoder 12 and the output line of a data write circuit and the voltage of the output line is fed back. Consequently, the voltage is surely raised at the time of selection and is surely reduced at the time of nonselection. Thus, the power consumption is reduced regardless of the constitution of inexpensive N-channel MOS transistors, and the voltage margin is increased and the write margin is improved.

2. 发明专利

JPS63268196A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63268196A
公开(公告)日：1988-11-04
申请号：JP10141987
申请日：1987-04-24
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： KATO HIDEO , IWAHASHI HIROSHI , ASANO MASAMICHI , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H02M3/07 , H03K3/356 , H03K17/06
摘要： PURPOSE:To obtain an integrated circuit provided with a sub-boosting circuit having of a high boosting efficiency by setting the absolute value of the threshold voltage of a first MOS transistor TR lower than the threshold voltage of a second MOSTR, and obtaining a boosted output from the output terminal of a selection circuit. CONSTITUTION:A boosted output VPP from a main boosting circuit 11 is supplied to the sub-boosting circuit 12 and a circuit 13 to be supplied. The circuit 12 consists of N-channel type MOSTRs Q1, Q2 and a MOST capacitor C1, and the gates are connected to the selection circuit 14. To the source of the TR Q1, the drain and the gate of the TR Q2 are connected, and to the source of the TR Q2, a node N1 is connected. To the connection point of the source of the TR Q1 and the drain and the gate of the TR Q2, one electrode of the capacitor C1 is connected, but to the other electrode of the C1, a clock pulse phiC from a clock generation circuit 15 is supplied. The circuit 13 comprises an N-channel type MOSTR Q3, and to the drain of the TR Q3, the output terminal of the circuit 11 is connected. By setting the absolute value of the threshold voltage of the TR Q1 lower than the threshold voltage of the TR Q2, the output potential of the circuit 12 can be boosted.

3. 发明专利

JPS6394714A GENERATING CIRCUIT FOR CONTROL PULSE SIGNAL 失效
公开(公告)号：JPS6394714A
公开(公告)日：1988-04-25
申请号：JP24032786
申请日：1986-10-09
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： KATO HIDEO , IWAHASHI HIROSHI , ASANO MASAMICHI , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： H03K3/037 , H03K17/22 , H03L1/00
摘要： PURPOSE:To output a control pulse signal having a desired pulse width to an internal circuit by outputting an inverting signal when a voltage proportional to a power voltage reaches a prescribed time and retarding the inverting timing of the inverted signal for a prescribed time. CONSTITUTION:When a potential of a node N3 being an output of a power voltage detection section 11 is inverted from a level '1' to a level '0', the potential of output nodes N5-N7 of inverter circuits 14-17 in a pulse generating section 12 are inverted in a way of chain reaction at a respective prescribed delay time sequentially from the potential set initially by capacitors C3-C6 attached to each output node. Thus, a control pulse signal having a pulse width corresponding to a period till the potential of the node N7 is inverted after a level of the power voltage reaches a prescribed voltage and having a pulse level nearly equal to the power voltage level in this case, is outputted.

4. 发明专利

JPS6384168A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6384168A
公开(公告)日：1988-04-14
申请号：JP23072386
申请日：1986-09-29
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： KATO HIDEO , IWAHASHI HIROSHI , ASANO MASAMICHI , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To implement high integration density in memory cell and uniformity in electric characteristics, by forming a very thin silicon oxide film in the inside of a floating gate electrode. CONSTITUTION:N-type impurities are implanted into a substrate 10 to form an N type region 13. A silicon oxide film 16 having a thickness of 100 Angstrom is formed at a part of the region 13. A silicon oxide film 17 having a thickness of about several hundreds of Angstrom is formed in another region. A polycrystalline silicon layer is deposited on the entire surface. This layer is used as a floating gate electrode 20 of each cell, and the electrode 20 is split into parts 20A and 20B. A silicon oxide film 22 having a thickness of about several hundreds of Angstrom is formed thereon. Then, a polycrystalline silicon layer is deposited. Thereafter, the lower film 22 and the polycrystalline silicon layer beneath the film 22 are selectively etched continuously. The electrode 20 and a control electrode 23 and the gate electrodes 21 and 24 are formed in a self-aligning manner. The shape of the planar pattern of the electrode 23 is made approximately equal to that of the gate electrode 20 in the away direction of a drain and a source in each memory.

5. 发明专利

JPH0268797A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0268797A
公开(公告)日：1990-03-08
申请号：JP22022688
申请日：1988-09-02
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSBAC COMPUTER SYSTEM CO LTD
发明人： IWAHASHI HIROSHI , FUJIMOTO TOSHIYUKI , NARITA AKIRA
IPC分类号： G11C17/00 , G11C5/14 , G11C8/08 , G11C16/06 , G11C16/12 , H03K17/10
摘要： PURPOSE:To increase a break-down voltage at a drain by impressing a voltage approximately at 0V to the gate of a first load transistor and impressing an intermediate voltage smaller than a power source and larger than 0V to the gate of a second load transistor when program data are '1'. CONSTITUTION:When a signal A is '0', a transistor 3 is turned off, and nodes B1 and B2 are charged up to a boosting voltage SW through transistors 6 and 5. On the other hand, when the signal A is '1', the transistor 3 is turned on, and for such a reason, by enlarging the conducting resistance of the transistor 5 sufficiently, the node B1 is made approximately at 0V, a transistor 7 is turned on, and the node B2 is made into a value lower than the power source of an ordinary action by the degree of a threshold voltage. Thus, since the voltage of the B2 of a second load transistor 22 is raised over 0V, the break- down voltage of the drain is raised by the degree that the voltage is raised over the break-down at the time of 0V.

6. 发明专利

JPS61173522A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS61173522A
公开(公告)日：1986-08-05
申请号：JP1469485
申请日：1985-01-29
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD
发明人： IWAHASHI HIROSHI , ASANO MASAMICHI , NARITA AKIRA
IPC分类号： H03K23/64 , H03K23/00 , H03K23/54
摘要： PURPOSE:To vary electric characteristics of a circuit after the manufacture and to improve the manufacture yield by controlling two transistors (TR) as switch means selectively on the basis of a control signal generated corresponding to the selective blowing of fuses formed inside previously. CONSTITUTION:A control signal generating circuit 20 generates complementary- level signals S and S' for switch control over a couple of transfer gates 14 and 16 after an integrated circuit is manufactured. When the oscillation frequency of a ring oscillation circuit 11 is at its specified value after the manufacture of the integrated circuit, a fuse 22 is not blown and the output of a counter 12 which divides the oscillation frequency of the ring oscillation circuit 11 by two is selected and outputted; when a parameter in the middle of a manufacture process varies to cause an increase in the oscillation frequency of the ring oscillation circuit 11, the fuse 22 is blown by a laser or other means and the output of the counter 12 is further frequency-divided by two through a counter 13 and outputted. Consequently, the oscillation frequency is set again newly even after the integrated circuit is completed and the manufacture yield is improved greatly.

7. 发明专利

JPH04146596A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04146596A
公开(公告)日：1992-05-20
申请号：JP26805790
申请日：1990-10-05
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSBAC COMPUTER SYSTEM CO LTD
发明人： KATO HIDEO , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06 , G11C29/00 , G11C29/06
摘要： PURPOSE:To detect a defective memory cell without increasing the test time nor the chip area by increasing the conductance of a voltage application means compared with that of a column line selection means. CONSTITUTION:The conductance gm1 of a test transistor TR 2 is set larger enough than the conductance gm2 of the column gate transistors CTr1 - CTrn. That is, if a defective cell is included in a main body memory, a column line BL connected to the defective cell has a short circuit to a row line WL or the line BL has a short circuit to the ground. Therefore the resistance RT of the TR 2 is set lower enough than the resistance Rr of the column gate transistor CTr by means of the TR 2. Thus the stress voltage can be applied without lowering substantially a potential. As a result, a defective memory cell is detected in a short test time without complicating a circuit nor increasing the chip area.

8. 发明专利

JPH02137361A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02137361A
公开(公告)日：1990-05-25
申请号：JP29196788
申请日：1988-11-18
申请人： TOSHIBA CORP , TOSBAC COMPUTER SYSTEM CO LTD
发明人： IWAHASHI HIROSHI , NARITA AKIRA , FUJIMOTO TOSHIYUKI
IPC分类号： H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/08 , H01L27/115
摘要： PURPOSE:To easily suppress a latch-up phenomenon by a method wherein semiconductor elements whose polarity is different from that of a circuit element generating a substrate current are arranged so as to sandwich a semiconductor element whose polarity is equal to that of the circuit element. CONSTITUTION:With reference to a pad 22, for bonding use, connected to an external output terminal, an N-channel transistor 1 is arranged at the inside of a chip 1 and a P-channel transistor 2 is arranged at the outside, i.e., on the side of a chip end (e). Since the P-channel transistor 2 is arranged on the side of the chip end (e), it is separated from an internal circuit by an amount of the pad region 22. As a result, even when a substrate current causing a latch-up is generated, a substrate resistance becomes large by an amount of a distance from the internal circuit; accordingly, a base current by a parasitic bipolar transistor is limited. Thereby, it is possible to enhance resistance to the latch-up.

9. 发明专利

JPS6069897A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6069897A
公开(公告)日：1985-04-20
申请号：JP16411283
申请日：1983-09-08
申请人： TOSHIBA KK , TOSHIBA MICRO CUMPUTER ENG , TOSUBATSUKU COMPUTER SYSTEM KK
发明人： MOMOTOMI MASAKI , IWAHASHI HIROSHI , ASANO MASAMICHI , MINAGAWA EISHIN , SUZUKI KAZUTO , NARITA AKIRA
IPC分类号： G11C17/00 , G11C16/06 , G11C16/12
摘要： PURPOSE:To improve the reliability of an E PROM provided with an internal boosting circuit by providing a boosted voltage switching circuit between an address decoder and a memory cell array and supplying a boosted voltage in the boosting circuit only to a selected row of the memory cell array and cutting off the boosted voltage to non-selected rows to prevent a current from being flowed out to the output stage of the address decoder. CONSTITUTION:A boosted voltage switching circuit 17 is provided in the output terminal of an address decoder 13, and a high voltage (for example, VH=20V) obtained by boosting a power source voltage is supplied to a selected row, for which the output of the decoder 13 is ''1'', of a memory cell array 11 in case of rewrite, and a read voltage approximating the power source voltage is supplied there in case of read; and zero voltage is supplied to left non-selected rows, for which the output of the decoder 13 is ''0'', without flowing-out of the current.

10. 发明专利

JPH0586075B2 失效
公开(公告)号：JPH0586075B2
公开(公告)日：1993-12-09
申请号：JP23072386
申请日：1986-09-29
申请人： TOSHIBA KK , TOSHIBA MICRO CUMPUTER ENG , TOSHIBA JOHO SHISUTEMU KK
发明人： KATO HIDEO , IWAHASHI HIROSHI , ASANO MASAMICHI , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792

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