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1. 发明专利

JPH10154770A MANUFACTURE OF CERAMIC PACKAGE 失效
公开(公告)号：JPH10154770A
公开(公告)日：1998-06-09
申请号：JP35197697
申请日：1997-12-08
申请人： TOSHIBA CORP
发明人： SAITO KAZUYOSHI , IWASE NOBUO
IPC分类号： H01L23/12 , H01L23/04 , H01L23/08 , H01L23/15
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a ceramic package of small heat resistance with high joint strength to a glass. SOLUTION: Firstly, the surface of a ceramic substrate 11 which is made of aluminum nitride and on which a semiconductor chip 16 is mounted is oxidized to form an oxide layer 13 of Al2 O3 , AIN-AI2 O3 , and 3Y2 O3 .5AI2 O3 . Then, a glass layer 14 is deposited on the oxide layer 13 on the substrate. Then, through a glass layer 18, a ceramic cap 19 is bonded to the oxide layer 18 on the substrate 11.

2. 发明专利

JPH01191436A FILM CARRIER 失效
公开(公告)号：JPH01191436A
公开(公告)日：1989-08-01
申请号：JP1448788
申请日：1988-01-27
申请人： TOSHIBA CORP
发明人： SAITO KAZUYOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To reduce stress in a lead upon temperature change to minimum value, and to obtain a film carrier in which is thermal fatigue breakage does not occur by forming optimum sectional shape of wirings on the carrier. CONSTITUTION:Leads 3 protruding continuously form wirings 2 formed on a polyimide base 1 are connected through projecting electrodes 5 to a semiconductor element 4. The relationship between the lead width (b) and the lead thickness (h) is set at least to h/b=0.35 or less. Thus, thermal stress generated in the lead can be set to a low stress value sufficiently resistive against lead breakage.

3. 发明专利

JPH0196942A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0196942A
公开(公告)日：1989-04-14
申请号：JP25499187
申请日：1987-10-09
申请人： TOSHIBA CORP
发明人： SUDO TOSHIO , TAKUBO TOMOAKI , SAITO KAZUYOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To make it easy to cope with increment of number of input terminals and high density by adopting film carrier system and by providing terminal resistor near a position where integrated circuit chip is mounted. CONSTITUTION:A hole for mounting integrated circuit chip 2 and a through hole 6 for forming terminal resistor are formed on a resin film 1 such as a long polyimide, copper foil is applied to both faces, and a lead wire 3 and grounding conductor 8 are formed on one side and the other, respectively. The lead wire 3 is formed radially from a position where the integrated circuit chip is mounted and is connected to a protruding electrode 4 on an integrated circuit chip 5. With a protruding electrode 4, Au is plated on a barrier metal such as Ti-W-Au, Sn ir Au is plated on the lead wire 3, and connection is made by applying heat and load to both. A terminal resistor 7 is laid previously within the penetration hole 6 which was provided neat the integrated circuit chip 5 and one terminal is connected to the lead wire 3 and the other is connected to the grounding conductor 8. The lead wire 3 which is connected to the high-speed signal input terminal is adjusted to a specified characteristics impedance and a terminal resistor 7 is also set to the same resistance.

4. 发明专利

JPS6414933A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6414933A
公开(公告)日：1989-01-19
申请号：JP16963987
申请日：1987-07-09
申请人： TOSHIBA CORP
发明人： TAKUBO TOMOAKI , SAITO KAZUYOSHI , SUDO TOSHIO
IPC分类号： H01L21/60
摘要： PURPOSE:To display the high speed performance of a chip in correspondence with the increase in number of input terminal and implementation of high density, by providing a lead wire, which is connected to the signal input terminal of an integrated circuit chip as a returning wire, which constitutes a feed through wire, and connecting a returning part and a bonding pad in a overlapped pattern. CONSTITUTION:A lead wire 4A forming an outgoing path is provided from an outer connecting terminal part 2 to the vicinity of a semiconductor circuit chip on a TAB board. A returning wire passes through the lead wire 4A and a lead wire 4B and returns to the external connecting terminal part. Thus a feed through wiring is formed with respect to the input terminal of a the chip. The lead wire 4 has a constant width d1. Ground conductors 2 and 3, which are set at a terminating potential VTT, are arranged with a constant interval d2 being provided. Thus, a coplanar transmission line is formed. The returning part has a concentric pattern, and the wire width d1 and the interval d2 are kept constant. Thus the coplanar transmission line having constant characteristic impedance is formed. A through hole is formed at the returning part, where the lead wire 4 draws an arc. Conductor layers 10 and 11 comprising Cu films, which are made of the same material for the lead wire 4, are connected to a bump electrode 9 of an input terminal pad 8 of the integrated circuit chip 7. The bump electrode 9 is formed by Au plating through a barrier metal layers of Ti-Ni-Pd and the like.

5. 发明专利

JPS6384127A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6384127A
公开(公告)日：1988-04-14
申请号：JP22821186
申请日：1986-09-29
申请人： TOSHIBA CORP
发明人： INABA MICHIHIKO , SUZUKI ISAO , IWASE NOBUO , SAITO KAZUYOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To provide a bump directly on an aluminum electrode without base metal with a whole bump or a surface layer formed of a metal which mainly contains at least two types of Zn, Cu, Sn or one type of them and at least one type of In, Bi and Cd. CONSTITUTION:Component elements for forming an eutectic crystal with aluminum or intermetallic compound by diffusing Zn, Sn or Cu in aluminum to form a reaction layer, and an alloy including In, Bi, Cd for reducing a hardness and easily plastically deforming by the mixture are used. This alloy film 2 is formed on the bump 11 of a taper 3, and bonded through the reaction layer 1 on an aluminum electrode 4 on a semiconductor chip 5. Or, the alloy 2 is bonded to the heat of the bump 11 provided with leads 20 adhered with an insulating tape, or the bump 7 is covered with the alloy 2, or the bump itself is formed of the alloy 2. According to this configuration, the bump of Zn, Sn, Cu which is impossible to be bonded due to high hardness can be softened to be easily bonded, and a device having high bonding reliability is obtained in response to a miniaturization.

6. 发明专利

JPS6358948A FORMATION OF SOLDER BUMP 失效
公开(公告)号：JPS6358948A
公开(公告)日：1988-03-14
申请号：JP20336486
申请日：1986-08-29
申请人： TOSHIBA CORP , KURODA DENKI KK
发明人： INABA NAOHIKO , IWASE NOBUO , SAITO KAZUYOSHI , HIRATA SEIICHI , GONDA MAKOTO , HATANO HAJIME
IPC分类号： H01L21/60
摘要： PURPOSE:To form a solder bump directly without incurring an erosion phenomenon of an electrode by a method wherein a covering layer to be destroyed by ultrasonic waves is formed on an electrode part and a location corresponding to the electrode part is brought into contact with molten solder so that ultrasonic waves can be applied to the molten solder or a substrate. CONSTITUTION:At a silicon wafer 11 an electrode 14 is formed on a silicon substrate 12 via an insulating film 13, the electrode 14 is not covered with a passivating film 15 coating the whole surface, and additionally a covering layer 16 is formed on the whole surface. A glass plate to which a double-faced adhesive tape for high-temperature use is glued is attached to the reverse side of the silicon wafer 11, and this assembly is then dipped into spouting molten solder 23 by keeping it in a vertical position. Then, an ultrasonic vibrator 25 is inserted into the molten solder 23 at a location near the silicon wafer 11, and ultrasonic waves are applied to the molten solder 23. Therefore, the covering layer 16 on the electrode 14 and a natural oxide film are removed and a mountain-like solder bump 17 is bonded directly on the electrode 14.

7. 发明专利

JPS6358945A FORMATION OF SOLDER BUMP 失效
公开(公告)号：JPS6358945A
公开(公告)日：1988-03-14
申请号：JP20331386
申请日：1986-08-29
申请人： TOSHIBA CORP
发明人： SATO MICHIO , INABA MICHIHIKO , SAITO KAZUYOSHI , HIRATA SEIICHI
IPC分类号： H01L21/60
摘要： PURPOSE:To realize the direct formation of a solder bump without providing a substrate metal by a method wherein ultrasonic waves are applied in such a way that an electrode part is brought into contact with molten solder containing dispersed solid particles so that the molten solder containing dispersed solid particles is attached selectively to the electrode by means of alloying. CONSTITUTION:After one face of a double-faced adhesive tape for hightemperature use has been attached to the reverse side of a silicon wafer 11, this assembly is attached to a glass sheet via the other face of the adhesive tape. The assembly is then dipped into spouting molten solder 23 by keeping it in a vertical position, and an ultrasonic vibrator 25 is inserted into the molten solder at a location near the silicon wafer 11 so that ultrasonic waves can be applied. As the type of solder, Pb-Sn eutectic solder which contains dispersed solid particles is to be used. Through this constitution, prior to this operation an electrode 33 is formed on a silicon substrate 31 via an insulating film 32, and the electrode 33 is not covered with a passivating film 34 which coats the whole surface. After the operation, a mountain-like solder bump 35 is bonded directly on the electrode 33.

8. 发明专利

JPS62149158A ELECTRONIC PART DEVICE 失效
公开(公告)号：JPS62149158A
公开(公告)日：1987-07-03
申请号：JP10482186
申请日：1986-05-09
申请人： TOSHIBA CORP
发明人： TANUMA CHIAKI , IWASE NOBUO , ONO TOMIO , SAITO KAZUYOSHI , KONDO TAKESHI , HENMI KAZUHIRO
IPC分类号： H01L41/09 , H01L23/467 , H01L41/08 , H05K7/20
摘要： PURPOSE:To cool an electronic-part package effectively, by attaching cooling means utilizing bimorph vibrators and the like to the package, in which electronic circuits are packaged as a unitary body. CONSTITUTION:A package main body 1 is constituted by a ceramic base 11, on which a semiconductor element 2 is mounted, and a ceramic cap 12. An inverted L type ceramic supporting stage 5 is bonded to the outside of the base 11 with a bonding agent such as epoxy resin so that thermally good conductivity is obtained. Piezoelectric elements 71 and 72 are stuck to both surfaces of vibrating plates 6 and bimorph vibrators are formed. Two cooling fans 8 having said structure are fixed to the stage 5 so that the package 1 is cooled from the upper part of the package 1. When an AC voltage is applied to the bimorph vibrators, the tip parts of the fans 8 are vibrated. Thus the surfaces of the base 11 is effectively cooled.

9. 发明专利

JPS62104143A FORMATION OF SOLDER BUMP 失效
公开(公告)号：JPS62104143A
公开(公告)日：1987-05-14
申请号：JP24433485
申请日：1985-10-31
申请人： TOSHIBA CORP
发明人： INABA MICHIHIKO , SAKURAI HISAHARU , SAITO KAZUYOSHI , IWASE NOBUO , UZAWA SUMIYO , SUZUKI ISAO
IPC分类号： H01L21/60
摘要： PURPOSE:To form a solder bump directly on an electrode simply, to facilitate wireless bonding to improve reliability, by applying ultrasonic waves to fused solder, braking a natural oxide film on the surface of the electrode, and selectively attaching the solder on the electrode. CONSTITUTION:A solder returning path 22 is formed in a solder bath 21, and fused solder 23 is contained. For example, double-surface adhesive tape for high temperature use is stuck to the back surface of a silicon wafer. The wafer is bonded to a glass plate and dipped in the jetting fused solder 23 in the longitudinal direction. An ultrasonic wave vibrator 25 is inserted in the fused solder 23 in the vicinity of the silicon wafer 11, and the ultrasonic waves are applied to the fused solder 23. During this soldering operation, nitrogen gas is made to flow around the wafer at a flow rate of 10l/min. Thus, oxidation of aluminum and thin in the solder, which are constituent elements of an electrodes is prevented. The electrode 33 is exposed out of a passivation film 34 before dipping. After the dipping, however, a solder bump 35 is directly bonded to the electrode 33 and the round shaped bump is formed by this operation.

10. 发明专利

JPS6281736A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6281736A
公开(公告)日：1987-04-15
申请号：JP22336085
申请日：1985-10-07
申请人： TOSHIBA CORP
发明人： SAITO KAZUYOSHI , IWASE NOBUO , TANUMA CHIAKI , ONO TOMIO
IPC分类号： H01L23/467
摘要： PURPOSE:To cool the respective package constituting a semiconductor device with extreme efficiency by disposing a cooling fin having a plurality of wings in the package of a semiconductor (chip) device having a large heat release amount, and simultaneously disposing a cooling fin between the wings of the cooling fin, thereby obtaining a highly efficient cooling apparatus. CONSTITUTION:The semiconductor device is composed by causing a cooling apparatus c to be adhered to the reverse side of the base 1a of a package consisting of aluminium nitride ceramics by means of an adhesive q composed of an epoxy resin, said cooling apparatus c consisting of a cooling fin 2 which has a comb-shaped cross section and is provided with four static wing f consisting of an aluminium plate-like body disposed with a predetermined spacing therebetween and in parallel with each other, and a cooling fin 3 disposed between static wings f. This fin 3 is provided with a brass dynamic wing 3c which is driven by a piezoelectric element 3b, and the heat is dissipated by applying a voltage of an appropriate frequency from a power supply line 3d to the piezoelectric element 3b (bimorph) so as to cause it to oscillate, which piezoelectric element is formed by stacking two piezoelectric bodies composed of lead titanate + lead zirconate + (alpha).

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