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1. 发明专利

JPH045856A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH045856A
公开(公告)日：1992-01-09
申请号：JP10591190
申请日：1990-04-21
申请人： TOSHIBA CORP
发明人： KUMAGAI JUNPEI , SAWADA SHIZUO
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To provide a structure adapted for high integration, high reliability, a high speed operation and a large capacity integration by isolating a bit line from a substrate with an insulating film. CONSTITUTION:Capacitors are formed at intersections between an n-type polysilicon layer 20 to become word lines and an n-type diffused layer 12 to become bit lines, and switching transistors are formed as vertical transistors along the side of a columnar region 16. Further, a cell plate electrode 30 is formed on the entire substrate 10. An insulating film 11 is further formed between the layer 12 constituting a bit line and the substrate 10. Thus, the bit line capacitance can be reduced, and a leakage current from the bit line to the substrate can be reduced. The layer 12 is substantially surrounded by the film 11, and an interlayer insulating film 22, and incident probability of alpha-rays etc., to the bit line or collecting probability of ionized carrier can be reduced.

2. 发明专利

JPH01217964A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01217964A
公开(公告)日：1989-08-31
申请号：JP4346888
申请日：1988-02-26
申请人： TOSHIBA CORP
发明人： KUMAGAI JUNPEI , YOSHIKAWA SUSUMU , SAWADA SHIZUO , MATSUMOTO YASUO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To realize the self-alignment formation of a very fine contact hole, by forming a third insulating film by forming a first thin hole in a second insulating film formed on a substrate, forming a second thin hole by using a mask in which the third film is left on the side wall of the thin hole, forming a fourth insulating film on the surface of the second thin hole, and eliminating the third insulating film. CONSTITUTION:After a silicon oxide film 29 and a first silicon nitride film 30 are deposited on the surface of a semiconductor substrate 1, resist 27 is spread thereon and patterned. By selectively eliminating the above films 29 and 30, a first thin hole 28 is formed. Next, the resist 27 is exfoliated, and a second silicon nitride film 31 is deposited, which is subjected to anisotropic etching and left on the side wall of the thin hole 28. By using the nitride films 30, 31 as masks, the substrate 1 is subjected to anisotropic etching, and a second thin hole 32 is bored, on the surface of which a silicon oxide film 33 is formed. By exfoliating the nitride films 30, 31, a contact hole 35 is formed. The width lcan be adjusted by the width l' of the nitride film 31 left on the side wall, i.e., the thicknesses of the first and the second nitride films, so that the width of 0.2-0.3mum can be easily obtained.

3. 发明专利

JPS63119574A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63119574A
公开(公告)日：1988-05-24
申请号：JP26502286
申请日：1986-11-07
申请人： TOSHIBA CORP
发明人： KUMAGAI JUNPEI , SHINOZAKI SATOSHI
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/08 , H01L29/78
摘要： PURPOSE:To improve junction breakdown strength, by implanting impurities into a source or drain region in mask alignment. CONSTITUTION:In the manufacturing process of a semiconductor integrated circuit having an MOS transistor in an input protecting circuit, the source or drain region of the MOS transistor in the input protecting circuit is formed by a mask alignment method. Thereafter an insulating film and a conductive film are laminated and formed. The films are patterned in a desired shape, and a gate insulating film 13 and a gate electrode 14 are formed. With these parts as masks, impurities are implanted, and the source and drain regions of at least another transistor are formed by a self-alignment method. Thus, the impurity concentration in the source or the drain is increased, diffusion resistance is decreased and junction breakdown power due to a drain current is increased. The radius of curvature at the curved junction part of the source or the drain is increased. Thus the electric field in said curved region is allevaited, and the junction breakdown strength can be improved.

4. 发明专利

JPS6140054A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：JPS6140054A
公开(公告)日：1986-02-26
申请号：JP16057184
申请日：1984-07-31
申请人： Toshiba Corp
发明人： KUMAGAI JUNPEI
IPC分类号： H01L27/10 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10829
摘要： PURPOSE:To improve an integration rate and to make it possible to operate in high rate, by arraying in multi-level a transistor Tr and a capacitor in a fine aperture and by employing conductive material with a low resistance in a word wire and a bit wire. CONSTITUTION:On a semiconductor substrate 101, element separating regions 102 are selectively formed, by which an element region is being separated. Moreover, on the surface of the element region, an oxidation film 103 is formed. On the regions 102, 103, a word wire 104 made of high conductive material is formed, and over the entire face an inter-layer insulating film 105 is formed. Moreover, a fine aperture reaching to the substrate 101 from the film 105 is formed in the element region. An insulating film 107 is formed on the inner wall faces of the aperture 106, in which single crystal Si doped with impurities is filled to form an electrode 108 with which a bit wire 109 is electrically connected. In this structure, a capacitor is defined by the substrate 101 and the side walls and botton of the fine aperture, and a transistor by the wire 104 and the side walls of the aperture 106.
摘要翻译：目的：为了提高积分率，并且可以高速率地运行，通过在晶体管Tr和微细孔径中的电容器的多电平排列，并且通过在字线和位中采用具有低电阻的导电材料线。构成：在半导体衬底101上，选择性地形成元件分离区域102，元件区域通过该元件分离区域被分离。此外，在元件区域的表面上形成氧化膜103。在区域102,103上形成由导电材料制成的字线104，并且在整个表面上形成层间绝缘膜105。此外，在元件区域中形成从膜105到达基板101的细孔。绝缘膜107形成在孔106的内壁面上，其中填充掺杂有杂质的单晶Si以形成电极108，位线109与电极108电连接。在该结构中，电容器由衬底101和细孔的侧壁和底部限定，并且通过线104和孔106的侧壁限定晶体管。

5. 发明专利

JP2001184374A INTEGRATED CIRCUIT ANALYSIS DEVICE 失效
公开(公告)号：JP2001184374A
公开(公告)日：2001-07-06
申请号：JP36707599
申请日：1999-12-24
申请人： TOSHIBA CORP
发明人： NIINA HIROSHI , KIJI JIYUNICHI , KUMAGAI JUNPEI , USAMI MASAMI , KAKINUMA HIDENORI
IPC分类号： G01R31/28 , G06F17/50 , H01L21/82 , H01L29/00
摘要： PROBLEM TO BE SOLVED: To calculate the operation (qualitative change of potential) of an integrated circuit without conducting difficult work on the calculation of the operation of the integrated circuit by electronic circuit simulation, which is strict circuit element extraction and strict decision of a circuit element parameter. SOLUTION: A layout graph extraction means 102 storing layout graph information to which information on a node and an arc as graph information are added of the integrated circuit, a potential transmission parameter rendering means 113 storing an electric characteristic variation rule where a method that the respective nodes electrically influence each other is individually described on the nodes and the arcs in an integrated circuit network, an initial condition setting means 108 giving the initial condition of layout graph information, a driving signal output means 107 giving the integrated circuit driving signal, and electric characteristics variation calculating means 111 and 106 calculating an electric behavior change on the nodes and the arc for the integrated circuit network initialized by the initial condition setting means in accordance with the electric characteristics variation rule are provided.

6. 发明专利

JPH0982904A DYNAMIC TYPE STORAGE DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0982904A
公开(公告)日：1997-03-28
申请号：JP23536295
申请日：1995-09-13
申请人： TOSHIBA CORP
发明人： KUMAGAI JUNPEI
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a DRAM which can reduce the area per unit cell and the failure due to imperfect bit line contact. SOLUTION: This dynamic storage device is formed via the following; an active area for an MOS transistor which is formed on a semiconductor substrate 10, a word line WL which is formed on a channel region via a gate insulating film 20 and has a gate electrode part G, a bit line BL which is formed in contact with a drain region, and interlayer insulating films 21, 22 on the first bit line and the word line. The device is provided with a capacitor electrode 6 which is formed in contact with a source region, a capacitor plate electrode 8 which is formed on the capacitor electrode via a capacitor insulating film 24 and has almost the same plane form as the capacitor electrode, and a second bit line/BL which is formed in contact with the upper surface of the capacitor plate electrode and makes a complementary pair with the first bit line.

7. 发明专利

JPH053206A OFFSET GATE TRANSISTOR AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH053206A
公开(公告)日：1993-01-08
申请号：JP20676991
申请日：1991-08-19
申请人： TOSHIBA CORP
发明人： KUMAGAI JUNPEI , MIZUNO TOMOHISA
IPC分类号： H01L21/336 , H01L27/088 , H01L29/423 , H01L29/51 , H01L29/78
摘要： PURPOSE:To provide a transistor of an offset gate structure having high driving capability. CONSTITUTION:A gate electrode 14 is formed on a gate insulator 12 above a substrate 10. Insulating films 16 are formed on sides of the gate electrode 14 on the substrate. Diffused source and drain regions 18 are formed in the substrate. Ends of the p-n junctions of the source and drain regions 18 are in contact with the interface between the insulating films 16 and the substrate. Offset regions 100 of the same conductivity type as the substrate are formed in the substrate under the insulating films 16. The insulating films 16 are composed of an insulating material having a higher dielectric constant than the gate insulator 12 so that a higher electric field may be applied to the offset regions. As a result, the offset regions can be inverted sufficiently, and the driving capability of the transistor is improved.

8. 发明专利

JPH01218056A MANUFACTURE OF SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH01218056A
公开(公告)日：1989-08-31
申请号：JP4347988
申请日：1988-02-26
申请人： TOSHIBA CORP
发明人： YOSHIKAWA SUSUMU , KUMAGAI JUNPEI , SAWADA SHIZUO , MATSUMOTO YASUO
IPC分类号： H01L23/522 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To prevent a short circuit between a conductive body for capacitor electrode use and a charge storage layer for capacitor use by a method wherein the conductive body for capacitor electrode use is covered with an oxide film when a conductive body for connection use is to be formed. CONSTITUTION:A field oxide film 2 is formed selectively on a P-type semiconductor substrate 1; a groove 3 is formed. Then, an insulating film 4 is formed; polycrystalline silicon 5 doped with phosphorus as an impurity is formed on it. Then, an insulating film 6 for capacitor use is formed on it. Furthermore, polycrystalline silicon 7 doped with phosphorus is formed on it; an oxide film 6 is formed on it. Then, the insulating film on a device region is removed; a MOS transistor for transfer gate use is formed. Then, an insulating film 14 is formed so as to cover a gate electrode 11. By this setup, the polycrystalline silicon 5 as a charge storage layer for capacitor use is connected electrically to an impurity diffusion layer 13 of the MOS transistor via polycrystalline silicon 8 in order to prevent a short circuit to a conductor for capacitor electrode use.

9. 发明专利

JP2000251495A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2000251495A
公开(公告)日：2000-09-14
申请号：JP5382699
申请日：1999-03-02
申请人： TOSHIBA CORP
发明人： NISHIMURA KO , KUMAGAI JUNPEI
IPC分类号： G11C11/401 , G01R31/28 , G11C29/00 , G11C29/04
摘要： PROBLEM TO BE SOLVED: To enable detecting existence of leak between a cell and a pass word line by electrical measurement in a DRAM having structure in which a pass word line is arranged near an accumulating electrode of a memory cell. SOLUTION: When a noticing cell Sx is at a bit line BLx side, first, '0' of data is written in a cell S of a bit line BLx side, also '1' of data is written in a cell S of a bit line/BLx side. And when data of the noticing cell Sx is read out, a word line WLx and a pass word line WLy are simultaneously selected by a test mode. At the time, when a potential of an accumulating electrode of the noticing cell Sx is boosted by leak from the pass word line WLy, a potential of the bit line BLx is made higher than that of the bit line /BLx, as data of the noticing cell Sx is read out as '1', a leak path 41 between the pass word line WLy and the bit line BLx can be specified.

10. 发明专利

JPH036857A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH036857A
公开(公告)日：1991-01-14
申请号：JP14277389
申请日：1989-06-05
申请人： TOSHIBA CORP
发明人： YOSHIKAWA SUSUMU , KUMAGAI JUNPEI , SHINOZAKI SATOSHI
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
摘要： PURPOSE:To suppress the difference in level between a memory cell part and a peripheral circuit part and facilitate formation and processing of a wiring by a method wherein a transistor has a channel region formed on the side surface of a trench which is formed in a semiconductor main surface along its thickness direction and source/drain regions formed on the semiconductor main surface and on the bottom of the trench and at least a part of a capacitor is formed in the trench. CONSTITUTION:As the switching transistor and stacking type capacitor of a memory cell are formed in a trench 103', the difference in level between the memory cell part and a peripheral circuit part can be suppressed. Owing to the suppression of the difference in level, the poor step coverage of, for instance, a silicide film which is used as a wiring 115 on the stepped part can be avoided. Therefore, formation and processing of the wiring 115 are facilitated.

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