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1. 发明专利

JP2005190604A Semiconductor defect analyzing device and defect mode classifying method using the same 审中-公开
标题翻译：半导体缺陷分析装置和使用其的缺陷模式分类方法
公开(公告)号：JP2005190604A
公开(公告)日：2005-07-14
申请号：JP2003432242
申请日：2003-12-26
申请人： Toshiba Corp , 株式会社東芝
发明人： KODAMA MASAMI
IPC分类号： G01R31/28 , G11C29/00 , G11C29/44 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To quicken the defect analysis of a semiconductor memory by automatically updating a defect mode criterion when the number of defects of the FMB data of the semiconductor memory is equal to or more than a threshold value.
SOLUTION: This semiconductor defect analyzing device is provided with a measured data memory device 3 for obtaining and storing the FBM data of a semiconductor memory, and a CPU 1 having a creating means for creating the defect mode criterion of the semiconductor memory, a calculating means for classifying defect modes to calculate the characteristics of the defect modes based on the FBM data stored in the measured data memory device 3, and an updating means for updating the defect mode criterion when the amount of characteristics is compared with the defect mode to find that its ratio is equal to or more than the threshold value of the defect mode criterion.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：当半导体存储器的FMB数据的缺陷数等于或大于阈值时，通过自动更新缺陷模式标准来加速半导体存储器的缺陷分析。解决方案：该半导体缺陷分析装置设置有用于获得和存储半导体存储器的FBM数据的测量数据存储装置3和具有创建半导体存储器的缺陷模式标准的创建装置的CPU 1，一种计算装置，用于根据存储在测量数据存储装置3中的FBM数据对缺陷模式进行分类以计算缺陷模式的特性;以及更新装置，用于在将特征量与缺陷模式进行比较时更新缺陷模式标准发现其比率等于或大于缺陷模式标准的阈值。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JPH0784561A METHOD OF CONTROLLING PICTURE DISPLAY 失效
公开(公告)号：JPH0784561A
公开(公告)日：1995-03-31
申请号：JP22874293
申请日：1993-09-14
申请人： TOSHIBA CORP
发明人： IMAI TORU , MURANAGA TETSUO , AKUTSU MASAAKI , KODAMA MASAMI
IPC分类号： G09G5/14
摘要： PURPOSE:To preserve a meaning of the plotting related to a window when the window is revised for a display picture by analyzing the correspondence between the plotting and the window, and also revising the related plotting when the window is revised. CONSTITUTION:This system is constituted of a window control part 10 and a plotting control part 11 and a plotting/window dealing means 7, a display means 8 and an instruction part 9. When the revision is generated in the window, it is received by a window information storage means 2 also, and the display request is issued to the display means 8 by a window revision means 3. Further, when the plotting is revised by a plotting revision means 6, the related window is retrieved referring to the plotting/window dealing means 7, and when the relevant window exists, it is revised. Then, by a plotting input means 4, the display request is issued to the display means 8, and when the window is revised by the window revision means 3, the plotting revision means 6, retrieves the plotting referring to the plotting/window dealing means 7, and revises the relevant plotting.

3. 发明专利

JPH0773144A DISPLAY COMMUNICATION RELAY METHOD 失效
公开(公告)号：JPH0773144A
公开(公告)日：1995-03-17
申请号：JP22035893
申请日：1993-09-06
申请人： TOSHIBA CORP
发明人： MURANAGA TETSUO , AKUTSU MASAAKI , IMAI TORU , KODAMA MASAMI
IPC分类号： G06F15/00 , G06F13/00
摘要： PURPOSE:To add the functions of writing and pointing without changing an application program by generating and outputting a display request transmitted to a display control means based on input events except for the prescribed kinds of the input events. CONSTITUTION:An input event request means 32 requests the input events except for the prescribed input events to an input event transmission program 22. The input event transmission program 22 transmits the events to an input event processing means 33, and the input event processing means 33 directly generates a display output request and transmits it to a display output request processing means 34. The display output request means 34 executes mediation for an output request processing program. Thus, the function for executing overwrite on a screen can be added without a process for changing the application program 24, and a cooperative work support environment can be realized by viewing the same screen.

4. 发明专利

JP2010192026A Failure analysis method, failure analysis system, and memory macro system 审中-公开
标题翻译：故障分析方法，故障分析系统和存储器宏系统
公开(公告)号：JP2010192026A
公开(公告)日：2010-09-02
申请号：JP2009034330
申请日：2009-02-17
申请人： Toshiba Corp , 株式会社東芝
发明人： KODAMA MASAMI
IPC分类号： G11C29/44 , G01R31/28
CPC分类号： G06F11/27 , G11C29/32 , G11C29/44
摘要： PROBLEM TO BE SOLVED: To generate an FBM (fail bit map) easily understandable for a user.
SOLUTION: A failure analysis method includes: a configuration information extraction process (S2) to extract configuration information including the number of normal cell areas and the number of spare cell areas arranged in a memory macro and the size of each cell area, from circuit design information; an electrical test results collection process (S5) to successively collect the electrical test results indicating whether each memory cell included in all of the cell areas inclusive of the normal cell areas and the spare cell areas arranged in the memory macro has a failure or not; two-dimensional coordinate value calculating processes (S8, S9) to convert arrangement information corresponding to the collection order of the electrical test results to a two-dimensional coordinate value based on the configuration information; and output processes (S10, S11) to display the electrical test results based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了生成用户容易理解的FBM（故障位图）。解决方案：故障分析方法包括：提取配置信息的配置信息提取处理（S2），该配置信息提取包括布置在存储器宏中的正常单元区域的数量和备用单元区域的数量以及每个单元区域的大小，从电路设计信息; 电测试结果收集处理（S5），以连续收集指示包括正常小区区域在内的所有小区区域中的每个存储单元和布置在存储器宏中的备用单元区域是否有故障的电测试结果; 二维坐标值计算处理（S8，S9），用于基于配置信息将与电测试结果的收集顺序相对应的布置信息转换为二维坐标值; 和输出处理（S10，S11），以基于二维坐标值显示电测试结果，使得可以区分正常单元区域和备用单元区域。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2002198431A SEMICONDUCTOR FAILURE ANALYSIS SYSTEM AND METHOD, AND RECORDING MEDIUM STORING SEMICONDUCTOR FAILURE ANALYSIS PROGRAM 失效
公开(公告)号：JP2002198431A
公开(公告)日：2002-07-12
申请号：JP2000396125
申请日：2000-12-26
申请人： TOSHIBA CORP
发明人： KODAMA MASAMI
IPC分类号： G01R31/28 , G06F17/50 , H01L21/66 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To form a network for use in semiconductor failure analysis efficiently and accurately. SOLUTION: A section for forming a network representing the layout structure of an integrated circuit by a plurality of nodes arranged at potential measuring points, lines interconnecting the nodes, and a potential transmission rate (τ) set on the line comprises a section 6 for setting nodes based on the layout structure, a section 7 for setting lines based on the layout structure, and the like, a section 8 for setting a potential transmission rate on the line based on the potential transmission coefficients of respective layers, means 9 for extracting parasitic element information at a possible failure point based on the layout structure, and the like, and means 10 for setting a parasitic line interconnecting the nodes or altering the potential transmission rate based on the parasitic element information.

6. 发明专利

JPH08256145A ELECTRONIC CONFERENCE ENTRY METHOD AND ELECTRONIC CONFERENC SYSTEM 失效
公开(公告)号：JPH08256145A
公开(公告)日：1996-10-01
申请号：JP5691695
申请日：1995-03-16
申请人： TOSHIBA CORP
发明人： KODAMA MASAMI , KIMURA TETSUO
IPC分类号： H04M3/56 , H04L12/18 , H04L12/54 , H04L12/58
摘要： PURPOSE: To simplify the procedures for entry and to avoid interruption by registering a conference terminal having an identifier as a participant to an electronic conference in the case that this identifier of a user is registered in an entry permitted user list. CONSTITUTION: A conference manager 3 registers identifiers or users, who can enter the conference without procedures for permission at the time of requesting the entry, and stores the entry permitted user list in a permitted user list storage part 34. When the use of the electronic conference system is started, a user gives the host name of a conference server to a communication line control part 23 on a conference terminal 2 and sets it between the conference terminal 2 and a conference information server 1. When receiving the entry request including the identifier of the user, the manager 3 registers the conference terminal 2 of the sent identifier of the conference terminal 2 as a participant to the electronic conference if this identifier of the user is registered in the entry permitted user list. Consequently, procedure for entry to the conference are simplified, and proceedings are not obstructed by procedures for permission of the user making an application for entry.

7. 发明专利

JP2011113622A Failure analysis method and failure analysis device 审中-公开
标题翻译：故障分析方法和故障分析装置
公开(公告)号：JP2011113622A
公开(公告)日：2011-06-09
申请号：JP2009270618
申请日：2009-11-27
申请人： Toshiba Corp , 株式会社東芝
发明人： KODAMA MASAMI
IPC分类号： G11C29/44
摘要： PROBLEM TO BE SOLVED: To generate an FBM (fail bit map) which achieves easy association with memory cells of an actual memory macro.
SOLUTION: Macro configuration information 407 which includes information on the number of I/Os in a memory macro and on the sizes of the I/Os, is extracted from circuit design information (S1). The sizes of cell array areas to be used are computed on the basis of the extracted macro configuration information 407, and dummy cell maps 411 are generated on the basis of the sizes and the number of lines of dummy cells arranged in the peripheries of the cell array areas to be used which are fixed for each memory macro (S2). The FBMs 413 of the memory macro are generated on the basis of the results 412 of electrical tests (S3). The generated dummy cell maps 411 and FBMs 413 are combined to generate composite maps (composite fail bit maps) 414 (S4). The cell array areas to be used and dummy cell areas output the generated composite maps 414 in an identifiable manner (S5).
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：生成实现与实际存储器宏的存储单元的容易关联的FBM（故障位图）。解决方案：从电路设计信息（S1）中提取包括关于存储器宏中的I / O数量和I / O大小的信息的宏配置信息407。基于提取的宏配置信息407来计算要使用的单元阵列区域的大小，并且基于布置在单元的周边中的虚拟单元的行的大小和数量来生成虚拟单元映射411 要为每个存储器宏固定的阵列区域（S2）。基于电测试（S3）的结果412生成存储器宏的FBM 413。所生成的虚单元映射411和FBM 413被组合以生成复合映射（复合故障位图）414（S4）。要使用的单元阵列区域和虚拟单元区域以可识别的方式输出生成的复合图414（S5）。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2000260844A SEMICONDUCTOR FAILURE ANALYSIS SYSTEM AND METHOD THEREFOR 失效
公开(公告)号：JP2000260844A
公开(公告)日：2000-09-22
申请号：JP5767499
申请日：1999-03-04
申请人： TOSHIBA CORP
发明人： KODAMA MASAMI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor failure analysis system for automatically adding a new combination of electrical test results to a semiconductor failure analysis decision table as needed. SOLUTION: An analysis system is provided with a decision table which associates electrical test result of a semiconductor element with a failure factor, a means for specifying the failure factor of the semiconductor element based on the decision table, and a means of automatically adding the combination, when the combination of the electrical test results which are not included in the decision table appears, when the failure factor is specified.

9. 发明专利

JPH0981713A RECORDING METHOD AND REPRODUCING METHOD FOR SCREEN DATA 失效
公开(公告)号：JPH0981713A
公开(公告)日：1997-03-28
申请号：JP23428895
申请日：1995-09-12
申请人： TOSHIBA CORP
发明人： KODAMA MASAMI , FUJINO TAKESHI , KIMURA TETSUO
IPC分类号： H04N5/78 , G06T1/00
摘要： PROBLEM TO BE SOLVED: To record data displayed on a screen from an arbitrary point of time by recording management data for displaying image data to be displayed on the screen at each specific recording point of time including recording start request time according to a recording start request and recording display output requests after the request time. SOLUTION: When the data recording start request is inputted to an input part 1, a window server 2 starts recording data, the recording start request is sent to a screen display data recording part 46 through an input event processing part 41 of a dummy server 4 and registered in a time control part 47 from the recording point of time. When the recording is started, a screen display data recording part 46 informs a screen display data acquisition part 44 and an image data acquisition part 45 of the start of the recording. Then an event request part 43 sends an acquisition request to the window server 2, and the contents of an image data holding part 23 and the contents of a management data holding part 24 are acquired and sent from an input event transmission part 21 to the dummy server 4, and sent to the screen display data recording part 46 and recorded in a recording part 6.

10. 发明专利

JP2008299953A Failure analyzing method of semiconductor memory and failure analysis system 审中-公开
标题翻译：半导体存储器故障分析方法和故障分析系统
公开(公告)号：JP2008299953A
公开(公告)日：2008-12-11
申请号：JP2007145085
申请日：2007-05-31
申请人： Toshiba Corp , 株式会社東芝
发明人： KODAMA MASAMI , IIZUKA YOSHIKAZU
IPC分类号： G11C29/44 , G11C29/56
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/1806
摘要： PROBLEM TO BE SOLVED: To easily prepare an FBM (fail bit map) by converting a logical address of a semiconductor chip with many memory macros mounted into a physical address.
SOLUTION: This failure analyzing method comprises the steps of: selecting a memory macro to be analyzed from many memory macros on one chip and inputting the type of the memory macro; reading an address bit map corresponding to the type from an address bit map database; inputting size information of the memory macro; using the size information and the address bit map, converting the logical address of a failure cell detected from a result measured by a tester into a physical address of a memory macro of standard arrangement and preparing a fail bit map of the standard arrangement; inputting arrangement information of the memory macro; and converting a physical address of the fail bit map at the standard arrangement into a physical address of the memory macro from the arrangement information and preparing a fail bit map.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过将具有安装到物理地址的许多存储器宏的半导体芯片的逻辑地址转换为容易地准备FBM（故障位图）。解决方案：该故障分析方法包括以下步骤：从一个芯片上的许多存储器宏中选择要分析的存储器宏，并输入存储器宏的类型; 从地址位图数据库读取与类型对应的地址位图; 输入存储器宏的大小信息; 使用所述尺寸信息和地址位图，将从由测试仪测量的结果检测到的故障单元的逻辑地址转换为标准布置的存储器宏的物理地址并准备所述标准布置的故障位图; 输入存储器宏的布置信息; 以及将所述标准布置处的所述故障位图的物理地址从所述布置信息转换为所述存储器宏的物理地址，并且准备故障位图。版权所有（C）2009，JPO＆INPIT

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