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1. 发明专利

JP2012174953A Semiconductor storage device, and method of manufacturing the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2012174953A
公开(公告)日：2012-09-10
申请号：JP2011036643
申请日：2011-02-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWAI BURANDO
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L45/1675 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor storage device capable of reducing a resistance of wires used for memory cell arrays.SOLUTION: A method of manufacturing a semiconductor storage device in accordance with one embodiment includes the following steps of: laminating a first wiring layer; laminating a memory cell layer above the first wiring layer; and laminating a stopper film for reducing a speed of a latter polishing step above the memory cell layer. In addition, the manufacturing method includes the following steps of: etching the stopper film, the memory cell layer, and the first wiring layer; burying the stopper film, the memory cell layer, and the first wiring layer by an interlayer insulating film, and then performing polishing until reaching the stopper film; and executing nitriding treatment on the stopper film and the interlayer insulating film to form an adjustment film and a block film on surfaces of the stopper film and the interlayer insulating film respectively. The manufacturing method includes a step of forming a second wiring layer above the adjustment film so as to intersect with the etched first wiring layer to allow memory cells to be arranged at the respective intersections.
摘要翻译：解决的问题：提供一种能够降低用于存储单元阵列的电线的电阻的半导体存储装置的制造方法。解决方案：根据一个实施例的制造半导体存储装置的方法包括以下步骤：层叠第一布线层; 在第一布线层之上层叠存储单元层; 并且层压用于降低在存储单元层上方的后一抛光步骤的速度的止动膜。此外，制造方法包括以下步骤：蚀刻阻挡膜，存储单元层和第一布线层; 通过层间绝缘膜掩埋阻挡膜，存储单元层和第一布线层，然后进行抛光直到到达阻挡膜; 对停止膜和层间绝缘膜进行氮化处理，分别在阻挡膜和层间绝缘膜的表面上形成调整膜和阻挡膜。该制造方法包括在调整膜上形成第二布线层以与蚀刻的第一布线层交叉的步骤，以使存储单元布置在相应的交点处。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2002299572A SEMICONDUCTOR DEVICE AND ITS FABRICATING METHOD 失效
公开(公告)号：JP2002299572A
公开(公告)日：2002-10-11
申请号：JP2001095975
申请日：2001-03-29
申请人： TOSHIBA CORP
发明人： KAWAI BURANDO , ITO HITOSHI , YABUKI SO , SHINOMIYA HIDEO , ITO EIJI
IPC分类号： H01L27/105 , H01L21/8246
摘要： PROBLEM TO BE SOLVED: To satisfy both large capacitance and fine patterning (high integration) of capacitors in a ferroelectric memory. SOLUTION: A first capacitor electrode 121 and a second capacitor electrode 122 sandwiching a ferroelectric film (capacitor dielectric film) 13 have faces (sandwiching faces) perpendicular to the major surface of an Si substrate 1. After a gate part 2, an insulation film 3 on the gate, source and drain 4 and 5, an interlayer insulation film 6, and a plug 8 are formed on the Si substrate 1, a sacrificial insulation film is deposited on the entire surface and trenches for burying the capacitor electrodes 121 and 122 are made therein. A conductive film 12 is then deposited on the entire surface and eventually removed by CMP except that in the trenches. Subsequently, the trench frame of sacrificial insulation film is removed by etching, ferroelectric 13 is deposited and then the upper surface is polished thus completing a semiconductor device. Since the faces of the electrodes sandwiching the ferroelectric are perpendicular to the substrate 1 and the direction of polarization is parallel with the plane of the substrate, element area is not increased even if the sandwiching face is increased.

3. 发明专利

JP2013197461A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2013197461A
公开(公告)日：2013-09-30
申请号：JP2012065335
申请日：2012-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWAI BURANDO
IPC分类号： H01L27/105 , H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L45/1253 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/1608 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device of resistance change type memory capable of reducing wiring resistance.SOLUTION: A semiconductor memory device of resistance change type memory comprises: a first conductive layer 63; a variable resistance layer 64; an electrode layer 65; a first liner layer 66; a stopper layer 67; and a second conductive layer 70. The variable resistance layer 64 is provided on the first conductive layer 63. The electrode layer 65 is in contact with an upper surface of the variable resistance layer 64. The first liner layer 66 is in contact with an upper surface of the electrode layer 65. The stopper layer 67 is in contact with an upper layer of the first liner layer 66. The second conductive layer 70 is provided on the stopper layer 67. As compared with the stopper layer 67, the first liner layer 66 is composed of a material having a high orientation influence cancellation property of a lower layer thereof.
摘要翻译：要解决的问题：提供能够降低布线电阻的电阻变化型存储器的半导体存储器件。解决方案：电阻变化型存储器的半导体存储器件包括：第一导电层63; 可变电阻层64; 电极层65; 第一衬里层66; 阻挡层67; 和第二导电层70.可变电阻层64设置在第一导电层63上。电极层65与可变电阻层64的上表面接触。第一衬层66与上层电极层65的表面。阻挡层67与第一衬垫层66的上层接触。第二导电层70设置在阻挡层67上。与阻挡层67相比，第一衬垫层 66由具有较低取向特性的材料构成。

4. 发明专利

JP2010103389A Method of manufacturing semiconductor memory 审中-公开
标题翻译：制造半导体存储器的方法
公开(公告)号：JP2010103389A
公开(公告)日：2010-05-06
申请号：JP2008275130
申请日：2008-10-27
申请人： Toshiba Corp , 株式会社東芝
发明人： IGUCHI SUNAO , BABA MASANOBU , TAKAHATA KAZUHIRO , NAKAJIMA FUMIHARU , MUKAI HIDEFUMI , EMA TATSUHIKO , KAWAI BURANDO , KADOTA KENICHI , KIKUTANI KEISUKE
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor memory high in accuracy of widths of line and space.
SOLUTION: The method of manufacturing the semiconductor memory includes steps of: forming a first pattern constituted of a silicon material film on a film to be worked; oxidizing both side surfaces and an upper surface of the first pattern to form a silicon oxide film and removing a part of the silicon oxide film formed on the upper surface to form a second pattern constituted of the silicon oxide films formed on both side surfaces; removing the first pattern to form a mask pattern constituted of the second pattern; and working the film to be worked, exposed from the mask pattern.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种高线性和空间宽度精度的半导体存储器的制造方法。解决方案：制造半导体存储器的方法包括以下步骤：在待加工的膜上形成由硅材料膜构成的第一图案; 氧化第一图案的两个侧表面和上表面以形成氧化硅膜并去除形成在上表面上的氧化硅膜的一部分，以形成由形成在两个侧表面上的氧化硅膜构成的第二图案; 去除第一图案以形成由第二图案构成的掩模图案; 并将电影工作，从面具图案中露出。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2011129737A Method of manufacturing semiconductor storage device, and semiconductor storage device 审中-公开
标题翻译：制造半导体存储器件的方法和半导体存储器件
公开(公告)号：JP2011129737A
公开(公告)日：2011-06-30
申请号：JP2009287323
申请日：2009-12-18
申请人： Toshiba Corp , 株式会社東芝
发明人： YAHASHI KATSUNORI , KUNIYA TAKUJI , MATSUSHITA TAKAYA , TANIGUCHI SHUICHI , KAWAI BURANDO
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor storage device configured such that loss of an etching mask is small and residues which may cause a short circuit between adjacent memory cells are not left, and to provide the semiconductor storage device.
SOLUTION: A columnar memory cell is formed by: forming a first groove extending in a first direction and forming first wiring 103 after forming a first wiring layer and a memory cell layer 104A on a semiconductor substrate 101; forming a thin film 161 on a sidewall of the first groove; burying an interlayer dielectric 105 in the groove to form a laminate; forming a second wiring layer on the laminate; forming a second groove 186 extending in a second direction and forming second wiring 106; removing the thin film 161 exposed from a bottom part of the second groove 186; and removing the memory cell layer 104A exposed from the bottom part of the second groove 186 up to an upper part of the first wiring layer. The thin film 161 is faster in etching rate than the interlayer dielectric 105 and removed before the part of an adjacent memory cell layer 104A.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体存储装置的方法，其被配置为使得蚀刻掩模的损耗小，并且可能导致相邻存储单元之间的短路的残留物不被留下，并且提供半导体存储设备。解决方案：柱形存储单元通过以下方式形成：在半导体衬底101上形成第一布线层和存储单元层104A之后，形成沿第一方向延伸的第一沟槽和形成第一布线103; 在第一槽的侧壁上形成薄膜161; 将沟槽中的层间电介质105埋入以形成层压体; 在层压板上形成第二布线层; 形成沿第二方向延伸并形成第二布线106的第二槽186; 移除从第二槽186的底部露出的薄膜161; 并且从第二槽186的底部露出的存储单元层104A去除到第一布线层的上部。薄膜161的蚀刻速度比层间电介质105更快，并且在相邻的存储单元层104A的部分之前去除。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2007207947A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007207947A
公开(公告)日：2007-08-16
申请号：JP2006023851
申请日：2006-01-31
申请人： Toshiba Corp , 株式会社東芝
发明人： TAKEUCHI WAKAKO , AKAHORI HIROSHI , KAWAI BURANDO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device containing a non-volatile semiconductor memory being capable of inhibiting an increase in the aspect ratio of a control gate electrode with the fining of an element, while being capable of inhibiting the increase in a leakage current between the control gate electrode and a charge storage layer.
SOLUTION: The semiconductor device has a semiconductor substrate 2, first insulating films 3 formed on the semiconductor substrate 2, the charge storage layers 4 formed on the first insulating films 3, and second insulating films 5 being formed on the charge storage layers 4 and using nitride films as uppermost layers. The semiconductor substrate further has the control gate electrodes 13 as single layers formed on the second insulating films 5 and composed of a metallic silicide.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种包含非易失性半导体存储器的半导体器件，其能够抑制元件的精细化时控制栅电极的纵横比的增加，同时能够抑制控制栅电极与电荷存储层之间的漏电流。解决方案：半导体器件具有半导体衬底2，形成在半导体衬底2上的第一绝缘膜3，形成在第一绝缘膜3上的电荷存储层4和形成在电荷存储层上的第二绝缘膜5 并且使用氮化物膜作为最上层。半导体衬底还具有形成在第二绝缘膜5上并由金属硅化物构成的单层的控制栅电极13。版权所有（C）2007，JPO＆INPIT

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