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1. 发明专利

JP2005208680A Active matrix type liquid crystal display 审中-公开
标题翻译：主动矩阵式液晶显示
公开(公告)号：JP2005208680A
公开(公告)日：2005-08-04
申请号：JP2005107474
申请日：2005-04-04
申请人： Toshiba Corp , Toshiba Electronic Engineering Corp , 東芝電子エンジニアリング株式会社 , 株式会社東芝
发明人： HANAZAWA YASUYUKI , YAMAMOTO KAYO , IZUKI YOSHIHARU , KITAZAWA TOMOKO , NAGAYAMA KOHEI , NAKAZATO MASAHIRO , TAKEBAYASHI KISAKO , IIZUKA TETSUYA
IPC分类号： G02F1/1339
摘要： PROBLEM TO BE SOLVED: To constitute an active matrix type liquid crystal display having favorable display performance with low electric power consumption by increasing the aperture rate of pixels.
SOLUTION: Three-color interlayer insulating films 9B, 9G, 9R and a light-shielding film 47 constituting a color filter layer are layered on a storage capacitor line 15, and the layers of the three-color interlayer insulating films 9B, 9G, 9R and the light-shielding film 47 are used as a spacer between an array substrate 2 and a counter substrate 3.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过增加像素的开口率，构成具有良好显示性能，低功耗的有源矩阵型液晶显示器。解决方案：构成滤色器层的三色层间绝缘膜9B，9G，9R和遮光膜47层叠在辅助电容线15上，并且三色层间绝缘膜9B， 9G，9R和遮光膜47用作阵列基板2和对置基板3之间的间隔物。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2003316850A Pattern layout method and device for liquid crystal display device, and medium with pattern layout program stored therein 审中-公开
标题翻译：用于液晶显示装置的图形布局方法和装置，以及存储有图案布局程序的介质
公开(公告)号：JP2003316850A
公开(公告)日：2003-11-07
申请号：JP2002124598
申请日：2002-04-25
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUKI YOSHIHARU
IPC分类号： G02F1/13 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a pattern layout device for a liquid display device capable of performing a precise liquid crystal device pattern layout in a short time.
SOLUTION: The signal waveform of the electric signal of a liquid crystal pattern layout is drawn in conformation to the liquid crystal pattern layout. A coordinate is extracted from the drawn signal waveform, and the electric signal is converted to a form of signal waveform usable in a liquid crystal circuit simulator by the conversion from the extracted coordinate to time and potential. The electric signal converted to the form of signal waveform usable in the liquid circuit simulator is stored in relation to the liquid crystal pattern layout. Since the liquid crystal pattern layout can be matched to the electric signal, the pattern layout can be designed in a short time without almost making a mistake.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种能够在短时间内执行精确的液晶装置图案布局的液晶显示装置的图案布局装置。解决方案：液晶图案布局的电信号的信号波形以液晶图案布局的形式绘制。从绘制的信号波形中提取坐标，并且通过从提取的坐标到时间和电位的转换，将电信号转换为可用于液晶电路模拟器中的信号波形的形式。转换成可用于液体循环模拟器的信号波形形式的电信号相对于液晶图形布局存储。由于液晶图案布局可以与电信号匹配，因此可以在短时间内设计图案布局，而几乎不会出错。版权所有（C）2004，JPO

3. 发明专利

JP2002367890A Method and apparatus for pattern layout and medium with pattern layout program stored therein 审中-公开
标题翻译：具有图案格局的方法和装置及其与存储的图案布局程序的介质
公开(公告)号：JP2002367890A
公开(公告)日：2002-12-20
申请号：JP2001171676
申请日：2001-06-06
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUKI YOSHIHARU
IPC分类号： G03F1/68 , G03F1/70 , H01L21/027 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To provide a pattern layout method wherein the enhancement of design accuracy, shortening of a designing period, and reduction of design error are made possible by creating an exposure pattern to be transferred onto a substrate by exposure.
SOLUTION: Part of each reticle pattern 15 which does not overlap a light shielding band pattern 16 is extracted, and an exposure pattern 23 to be transferred onto a substrate by an aligner is created. If there is such a defect that the light shielding band pattern 16 overlaps a reticle pattern 15, that can be immediately detected from the exposure pattern 23. Thus, the enhancement of design accuracy, shortening of a designing period, and reduction of design error are possible.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供一种图案布局方法，其中通过产生通过曝光转印到基板上的曝光图案，可以实现提高设计精度，缩短设计周期和减少设计误差。解决方案：提取不与遮光带图案16重叠的每个掩模版图案15的一部分，并且产生通过对准器转印到基板上的曝光图案23。如果存在遮光带图案16与掩模版图案15重叠的缺陷，则可以从曝光图案23立即检测。因此，设计精度的提高，设计周期的缩短和设计误差的减少是可能。

4. 发明专利

JP2000114387A PATTERN LAYOUT DEVICE, ITS METHOD AND STORAGE MEDIUM READABLE VIA COMPUTER AND STORING PATTERN LAYOUT PROGRAM 失效
公开(公告)号：JP2000114387A
公开(公告)日：2000-04-21
申请号：JP28682198
申请日：1998-10-08
申请人： TOSHIBA CORP
发明人： IZUKI YOSHIHARU
IPC分类号： H01L21/3205 , G02F1/136 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To reduce the design period of a circuit pattern by adding a contact pattern to a section which is electrically connected on a wiring pattern in parallel and changing the wiring pattern automatically following the layout of the added contact pattern. SOLUTION: The name of a layer forming a wiring 11, a wiring 12 and a contact 14 on a CAD software and a minimum line width and a minimum line interval, etc., of a pattern in each layer are inputted. Then, a pattern of each of the wiring 11, the contact 14 and the wiring 12 is generated, self- judgment is carried out whether or not the wiring 11 and the wiring 12 are electrically connected to the contact 14, and at the same time, each part is recognized according to a software. A pattern of the contact 14 is added in parallel on a pattern of each of the wirings 11, 12 by the software and a pattern of the wiring 11 is changed following the of layout the pattern of the contact 14.

5. 发明专利

JPH11272737A Pattern layout method, pattern layout device and record medium therefor 失效
标题翻译：模式布局方法，图案布局设备及其记录介质
公开(公告)号：JPH11272737A
公开(公告)日：1999-10-08
申请号：JP7815798
申请日：1998-03-25
申请人： Toshiba Corp , 株式会社東芝
发明人： IZUKI YOSHIHARU , NAKAZATO MASAHIRO , KITAZAWA TOMOKO
IPC分类号： G06F17/50 , G02F1/136
摘要： PROBLEM TO BE SOLVED: To easily generate a basic pattern by a CAD and to accurately and easily provide a prescribed pattern by moving an area specifying range equivalent to the size of the basic pattern in an optional direction in matrix patterns and segmenting an appropriate pattern including all the elements of the basic pattern surrounded by the area specifying range as the basic pattern.
SOLUTION: In a storage part on the CAD, the data 21 of a source pattern and the data 22 of the 1-dot pitch are set. Then, for instance, a 3×3 pattern for which 9 pieces of the source patterns are arrayed is formed (S1). An area specifying pattern is moved on the matrix pattern and the basic pattern of 1 dot is decided (S2). The pattern of the respective elements for constituting the basic pattern of 1 dot is recognized (S3) and a signal line pattern adjacent to the basic pattern of 1 dot is recognized (S4). An influence amount given to a display picture element electrode by the fluctuation of the video signals of a signal line is calculated (S5) and a calculated result 23 is held.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：为了容易地通过CAD生成基本图案，并且通过以矩阵模式移动与任选方向上的基本图案的尺寸相当的区域指定范围，并且分割适当的图案，准确且容易地提供规定图案，包括基本模式的所有元素被区域指定范围包围为基本模式。解决方案：在CAD的存储部件中，设置源图案的数据21和1点间距的数据22。然后，例如，形成排列有9个源图案的3×3图案（S1）。区域指定图案在矩阵图案上移动，并且确定1点的基本图案（S2）。识别用于构成1点的基本图案的各个元件的图案（S3），并且识别与1点的基本图案相邻的信号线图案（S4）。计算通过信号线的视频信号的波动给显示像素电极的影响量（S5），并且保持计算结果23。

6. 发明专利

JPH1039336A ACTIVE MATRIX TYPE LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH1039336A
公开(公告)日：1998-02-13
申请号：JP19758296
申请日：1996-07-26
申请人： TOSHIBA CORP
发明人： KITAZAWA TOMOKO , HANAZAWA YASUYUKI , IZUKI YOSHIHARU , NAGAYAMA KOHEI
IPC分类号： G02F1/136 , G02F1/1362 , G02F1/1368 , H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a liquid crystal display device which has a high opening rate and excellent display grade. SOLUTION: The array substrate of this device is arrayed with signal lines 33 on a transparent insulating substrate. Scanning lines 38 are so arrayed as to intersect orthogonally with the signal lines 33. Pixel electrodes 44 are arranged in a matrix form via interlayer insulating films above the regions segmented by the signal lines 33 an the scanning lines 38. Thin-film transistors 21 are formed near the respective intersected points of the signal lines 33 and the scanning lines 38. The signal lines 33 are connected to the drain electrodes 40 of these transistors, the pixel electrodes 44 via contact holes 43 to the source electrodes 31 and the scanning lines 38 to the gate electrodes 37, respectively. Shielding electrodes 39 are arranged via insulating films above the signal lines 33 along the signal lines 33. These shielding electrodes 39 are connected to the adjacent scanning lines 38b.

7. 发明专利

JP2003076733A Method for pattern layout, apparatus therefor and recording medium with program for the same recorded thereon 审中-公开
标题翻译：用于图案布局的方法，其装置和记录介质的程序与其记录的程序
公开(公告)号：JP2003076733A
公开(公告)日：2003-03-14
申请号：JP2001358253
申请日：2001-11-22
申请人： Toshiba Corp , Toshiba Electronic Engineering Corp , 東芝電子エンジニアリング株式会社 , 株式会社東芝
发明人： OI AKIRA , IZUKI YOSHIHARU
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a method for pattern layout capable of efficiently connecting and wiring between terminals to be connected.
SOLUTION: This method lays out array patterns with predetermined target distances and plots wiring to connect corresponded terminals, then the method determines whether a result of the wiring satisfies a predetermined design rule, and adds predetermined step distances to intervals of both patterns and re-lays out the array patterns when the result does not satisfy the design rule. The method repeats re-layouts and the wiring among the terminals to satisfy the design rule, so that operations are extensively reduced in time and efficient pattern layouts are allowed.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种能够在要连接的终端之间有效连接和布线的图案布局的方法。解决方案：该方法规定了预定目标距离的阵列图案，并绘制了连接相应端子的布线，然后该方法确定布线的结果是否满足预定的设计规则，并将预定的步距添加到两种图案的间隔和重新铺设当结果不满足设计规则时，排除阵列模式。该方法重复重新布局和终端之间的接线以满足设计规则，从而大大减少了操作，并允许有效的模式布局。

8. 发明专利

JP2001344301A METHOD AND DEVICE FOR LAYOUTING PATTERN AND COMPUTER- READABLE MEDIUM WITH PATTERN LAYOUT PROGRAM STORED THEREON 失效
公开(公告)号：JP2001344301A
公开(公告)日：2001-12-14
申请号：JP2000166171
申请日：2000-06-02
申请人： TOSHIBA CORP
发明人： IZUKI YOSHIHARU
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , G03F1/08
摘要： PROBLEM TO BE SOLVED: To provide a pattern layout device that effectively and precisely extracts a shape and a critical area value from patterns that is a parameter required for calculating the yield of the wiring pattern. SOLUTION: The pattern layout device recognizes patterns 21A and 21B from patterns drawn on a CAD. The pattern layout device finds critical areas from each state of the wiring patterns of 21A and 21B accurately and effectively, which are overlapped with and caused by a dust pattern 22 at different places.

9. 发明专利

JP2000020569A METHOD FOR CHECKING DESIGN ROUTINE 失效
公开(公告)号：JP2000020569A
公开(公告)日：2000-01-21
申请号：JP18652898
申请日：1998-07-01
申请人： TOSHIBA CORP
发明人： NAKAZATO MASAHIRO , IZUKI YOSHIHARU
IPC分类号： G02F1/13 , G02F1/136 , G02F1/1368 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To reduce the capacity of a medium to be used for recording or storing patterns and to shorten the time required for checking operation by checking the design rules of an extracted dot pattern of one-dot size. SOLUTION: A pixel area 2 in an array pattern 1 is specified. Then, the one-dot size of a dot pattern of each pixel in the area 2 is inputted and the dot pattern of one-dot size is extracted, and design rules such as the line width and line interval of the extracted one-dot pattern are checked. When an error is judged in the design rule check of the pixel area 2, the error part is corrected, the array pattern 1 is reprepared and processing is repeated again from the specification of a pixel area 2. When there is no error, the design rule check of the pixel area 2 is completed. Then, the design rules of a non-pixel area 3 are checked.

10. 发明专利

JPH09120082A ACTIVE MATRIX TYPE LIQUID CRYSTAL DISPLAY DEVICE 失效
公开(公告)号：JPH09120082A
公开(公告)日：1997-05-06
申请号：JP27606795
申请日：1995-10-25
申请人： TOSHIBA CORP
发明人： INADA KATSUHIKO , IZUKI YOSHIHARU
IPC分类号： G02F1/136 , G02F1/1368
摘要： PROBLEM TO BE SOLVED: To obtain a sufficient contact without lowering opening rate by forming the contact parts between source electrodes and display pixel electrodes by utilizing the outer peripheral parts of the display pixel electrodes. SOLUTION: Scanning lines 50 and signal lines 51 continuous across the respective pixels are arrayed in a matrix form and thin-film transistors(TFTs) 52 are formed in the crossing point parts thereof. These TFTs 52 are constituted of gate electrodes integral with the scanning lines 50 and source electrodes 7 and drain electrodes 8 formed to face each other via gate insulating films and semiconductor layers thereon. In this case, the junctures of the source electrodes 7 and the display pixel electrodes 9 are so formed as to enclose the display pixel electrodes 9 along the three sides of the display pixel electrodes 3 and have the parts along the longitudinal direction of the channels of the TFTs 52 and the parts 10 extending to both sides of the display pixel electrodes 9 along the transverse direction of the channels. Further, the junctures 10 are so disposed as to be superposed on storage capacitance electrodes 3.

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