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1. 发明专利

JPS58147879A CONTROL SYSTEM OF CACHE MEMORY 失效
公开(公告)号：JPS58147879A
公开(公告)日：1983-09-02
申请号：JP2873182
申请日：1982-02-26
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： SAKAUCHI AKIRA , SUZUKI SHIYOUHEI
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10 , G06F12/12
摘要： PURPOSE:To prevent even a part with high accessing frequency in a cache memory from being substituted and to provide flexibility when such as the position in the memory is changed by using plural cache memory units selectively according to the contents of a specifying field. CONSTITUTION:A figure shows a circuit which generates memory addresses by using segment descriptors and a central processing unit 400 is equipped with a segment register group 40 for holding several descriptors. During memory address generation, a segment number is supplied to a line 46 and an in-segment address is also supplied to a line 45. A base 41 is supplied to an adder 47 and added to said in-segment address and the sum is set in a memory address register 51. A size 42 is supplied to a comparator 48 and used to make a size check on said in-segment address. The contents of a cache specifying field 44 read out simultaneously are set in a register 52.

2. 发明专利

JPS57196357A DATA PROCESSOR 失效
公开(公告)号：JPS57196357A
公开(公告)日：1982-12-02
申请号：JP8085081
申请日：1981-05-29
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： SAKAUCHI AKIRA
IPC分类号： G06F9/42 , G06F9/445 , G06F9/46 , G06F9/48
摘要： PURPOSE:To get rid of dead reload and shunting of CPU information in case of reinterruption after having returned from interruption, and to execute it at a high speed, by deciding whether a request which newly becomes receivable exists or not, by program status word information read out from a stack which has not been reloaded yet. CONSTITUTION:Instruction inhibiting information is fetched from a register 61 for temporarily holding a program status word PSW information read out from a stack before it is reloaded to a PSW register, by which an interruption request which becomes receivable newly exists or not is tested. From this register 61, a data of a bit position corresponding to an interruption inhibiting mode flag of the PSW is fetched to a line 63, its data is inputted to a selector 62 together with a signal fetched to a line 11 from an interruption inhibiting mode flag of the present PSW, and one of them is outputted. Subsequently, in an output 65, whether an interruption request which newly becomes receivable exists or not can be decided by PSW information before reloading, read out from the stack which has not been reloaded yet.

3. 发明专利

JPS5624643A DATA COMPARING DEVICE 失效
公开(公告)号：JPS5624643A
公开(公告)日：1981-03-09
申请号：JP10002579
申请日：1979-08-06
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： HASHIMOTO YASUICHI , SAKAUCHI AKIRA
IPC分类号： G06F7/02
摘要： PURPOSE:To realize the efficient numerical value comparison processing by deciding the numerical value by the column number of the number such as ''5'' and ''10'' or the comparison of only the uppermost columns such as ''19'' and ''20''. CONSTITUTION:In CPU1, after the start of execution of the order, as a required information for the execution, in the length registers 4, 5, the length of the respective data (a), (b) and in the exponent register 6, 7, the digits of the respective data (a), (b) are prepared, and the symbols of the data are identified by the symbol identification device 8 and the symbols of the respective data (a), (b) are set at FF19, 10. Then, the the column number of zero continuing from the uppermost columns accumulated by the reading zero counter 11 is subtracted from the length of the data 4, 5 which is designated by the subtractor, and from the subtractor 12, a substantial column number of the data is output. Further, with respect to this output, the corresponding digits 6, 7 are added by the adder 13 and from the adder 13, the substantial column number of the data is putput.

4. 发明专利

JPS54112140A INFORMATION PROCESSOR 失效
公开(公告)号：JPS54112140A
公开(公告)日：1979-09-01
申请号：JP1908678
申请日：1978-02-23
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： YASHIKIDA HIROMI , SATOU FUMITAKA , SAKAUCHI AKIRA , WAKAI TETSUYA
IPC分类号： G06F15/00 , G06F13/00
摘要： PURPOSE:To reduce the modification of operating system OS by equipping integrated real-time processing system TDS with a FF which can be set only in a mode with its access region to a main memory unlimited. CONSTITUTION:Operating system OS is executed mainly in master mode 70 and access to the entire region of the main memory is possible while user programs are executed in slave mode 71. Immediately before the control moves from OS in mode 70 to TDS subsystem control program TED, an instruction of setting the FF of TFEF300 is sent out so as to set TDEF300. At the same time when the control moves to TDE mode 73, mode 71 becomes effective and AND circuit 301 sends out signal 302, so that the control will move from mode 73 to transaction process routine TPR mode 72. In this way, modes can be changed through hardware and the modification of OS is reduced, thereby making it possible to reduce the overhead.

5. 发明专利

JPS51141542A METHOD OF SEGMENTATION 失效
公开(公告)号：JPS51141542A
公开(公告)日：1976-12-06
申请号：JP6573475
申请日：1975-05-31
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： MURAYAMA MASAKI , SAKAUCHI AKIRA , UCHIDA YOSHIAKI
IPC分类号： G06F12/10 , G06F13/00
摘要： PURPOSE:To provide an efficient addressing in an information processor utilizing two dimensional address in segmentation method irrespective of associated memory.

6. 发明专利

JPS6019536B2 失效
公开(公告)号：JPS6019536B2
公开(公告)日：1985-05-16
申请号：JP1908578
申请日：1978-02-23
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： YASHIKIDA HIROMI , SATO FUMITAKA , SAKAUCHI AKIRA , WAKAI TETSUYA
IPC分类号： G06F15/00 , G06F12/00 , G06F12/02 , G06F13/00

7. 发明专利

JPS58146944A PROCESSOR FOR INFORMATION 失效
公开(公告)号：JPS58146944A
公开(公告)日：1983-09-01
申请号：JP2873282
申请日：1982-02-26
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： SAKAUCHI AKIRA
IPC分类号： G06F9/22 , G06F9/30 , G06F9/48 , G06F15/16 , G06F15/177
摘要： PURPOSE:To end the execution of an instruction after the time specified by a program, by executing the instruction stored in a main storage successively, and continuing the execution until a value applied by the instruction reaches a previously fixed value by the increment or decrement of the value. CONSTITUTION:Receiving an NOP (NO.OPERATION) instruction, a step 41 shifts the contents of the lower byte of the instruction to a work register TEMP in a processor. Subsequently steps 42, 43 execute the decrement of the contents in the TEMP and end the instruction at the time when the contents of the TEMP is turned to ''0''. The required time up to the end of the instruction is set up by the internal cycle time required for the execution of the steps 42, 43. Consequently the execution of the instruction can be end after the time specified by the program.

8. 发明专利

JPS5711385A DISPLAY UNIT 失效
公开(公告)号：JPS5711385A
公开(公告)日：1982-01-21
申请号：JP8544480
申请日：1980-06-24
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： SAKAUCHI AKIRA , TERASAWA MICHIYUKI
IPC分类号： G09G5/22 , G06F3/033 , G06F3/14 , G06F17/21 , G09G1/06 , G09G5/00

9. 发明专利

JPS5599654A MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS5599654A
公开(公告)日：1980-07-29
申请号：JP723679
申请日：1979-01-26
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： SAKAUCHI AKIRA
IPC分类号： G06F9/22 , G06F9/28
摘要： PURPOSE:To secure the control for the execution step length of the microprogram by loading the contents of the register which specify the execution time of the next microstep via a certain microstep. CONSTITUTION:One bit C in microorder register 301 is supplied to register 340 through execution of the microstep of register 301. In case the output of register 340 is 0, the microstep length is decided by delay circuit 111 and then by delay circuit 113 in case the output is 1 respectively. In case the extension is desired for the execution time duration of the second microstep via the first microstep, bit C in the microorder is turned to 1 at the first microstep.

10. 发明专利

JPS54112139A INFORMATION PROCESSOR 失效
公开(公告)号：JPS54112139A
公开(公告)日：1979-09-01
申请号：JP1908578
申请日：1978-02-23
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： YASHIKIDA HIROMI , SATOU FUMITAKA , SAKAUCHI AKIRA , WAKAI TETSUYA
IPC分类号： G06F15/00 , G06F12/00 , G06F12/02 , G06F13/00
摘要： PURPOSE:To reduce the overhead of integrated real-time processing system TDS by providing a 1st mode with its access region to a main memory unlimited and 2nd and 3rd modes with access regions limited. CONSTITUTION:Operating system OS operates in master mode 70 and can make access to all addresses on the main memory. User programs and TDS subsystem control programs TDE are executed in slave mode 71, and transaction process routine TPR is in TPR mode 72. In mode 71, access to only one continuous region on the main memory can be attained according the setting of a base address register. In mode 72, access to only two regions 9B and 9C on the main memory can be attained, and a change from mode 71 to mode 72 is made by a TST instruction. At the time of transition between TED and TPR, therefore, the need for the interposition of a master mode program is eliminated and the overhead is reduced greatly, so that the capacity of TDS will improve.

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