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1. 发明专利

JP2010219477A Method of wiring substrate with electronic component incorporated therein 有权
标题翻译：将基片与电子元件连接的方法
公开(公告)号：JP2010219477A
公开(公告)日：2010-09-30
申请号：JP2009067639
申请日：2009-03-19
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KOBAYASHI TOSHIO , ARAI SUNAO , YAMANO KOJI
IPC分类号： H05K3/46 , H01L23/12 , H05K3/38
CPC分类号： H01L24/97 , H01L21/568 , H01L24/96 , H01L2224/04105 , H01L2224/08145 , H01L2224/19 , H01L2224/73267 , H01L2924/01322 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/18162 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To simplify a process, to miniaturize wiring, and to relatively simply achieve further high-density mounting when manufacturing a wiring substrate with a semiconductor element or the like incorporated therein. SOLUTION: A member composed by forming bumps 43 each having a projecting part on electrode pads 41 of a substrate 40A, and bringing a sheet-like member 51 into press contact with an insulation layer 44 to expose partial parts of the projecting parts 43b to the upper surface of the insulation layer 44 is segmented to provide electronic components 40. The electronic components 40 are rearranged in a second insulation layer and rewiring is executed. Rewiring is further executed to a member composed by forming a third insulation layer (in a semi-cured state) covering the insulation layer 44, thereafter superposing a first structure with a conductor to be connected to the projecting parts 43b through the rewiring formed therein on a second structure manufactured through a process similar to that of it, and thermally curing the third insulation layer to be integrated. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了简化工艺，使布线小型化，并且在制造其中结合有半导体元件等的布线基板时相对简单地实现进一步的高密度安装。解决方案：通过在基板40A的电极焊盘41上形成有突出部分的凸块43构成的部件，并且使片状部件51与绝缘层44压接，以露出突出部分的部分部分 43b到绝缘层44的上表面被分段以提供电子部件40.电子部件40被重新布置在第二绝缘层中，并且执行重新布线。通过形成覆盖绝缘层44的第三绝缘层（处于半固化状态），然后将第一结构与通过其中形成的重新布线连接到突出部43b的导体重叠，通过与其类似的工艺制造的第二结构，并且热固化第三绝缘层以便整合。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010153497A Molding method and molding apparatus 审中-公开
标题翻译：成型方法和成型设备
公开(公告)号：JP2010153497A
公开(公告)日：2010-07-08
申请号：JP2008328356
申请日：2008-12-24
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KURASHIMA NOBUYUKI , KOBAYASHI TOSHIO
IPC分类号： H01L21/56 , B29C33/68 , B29C39/10 , B29C39/26 , B29C45/02 , B29L31/34
CPC分类号： B29C45/14655 , B29C45/0025 , B29C45/02 , B29C45/56 , B29C45/77 , B29C2945/76498 , B29C2945/76735 , B29C2945/76765 , B29C2945/76859 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To solve the problem of a conventional molding method in which uniform charging of melting mold resin is difficult while connection of solder balls is maintained in a space part of a first wiring board and a second wiring board.
SOLUTION: A semiconductor device where the second wiring board 16 corresponding to the first wiring board is connected to a loading face of a substrate 11 on which a plurality of first wiring boards are formed by the solder ball 18 is inserted into a cavity 32. A mold where a die plate 34 abutting on the second wiring board 16 through a release film 31 independently approaches or leaves the second wiring board 16 is used. With respect to the second wiring board 16, a first pressure permitting enlargement with a pressure of melting mold resin with which an interval between the substrate 11 and the second wiring board 16 is filled is added to the die plate 34 by a spring 36. An air gap between the substrate 11 and the second wiring board 16 is filled with mold resin. A second pressure higher than the first pressure is added to the second wiring board 16 from the die plate 34 abutting on stoppers 40 and 40 so as to prevent connection of the solder ball 18 from being peeled off. Mold resin is injected into the cavity 32.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题为了解决难以在第一配线基板和第二配线基板的空间部分保持连接焊球的情况下难以均匀充电熔融树脂树脂的常规成型方法的问题。解决方案：将与第一布线板相对应的第二布线板16连接到其上通过焊球18形成有多个第一布线板的基板11的装载面的半导体装置插入到空腔使用通过离型膜31独立地接近或离开第二配线板16的模板34与模板34抵接的模具。对于第二配线基板16，通过弹簧36将与基板11和第二配线基板16之间的间隔填充的熔融模塑树脂的压力允许扩大的第一压力加入到模板34中。衬底11和第二配线板16之间的空气间隙填充有模制树脂。比第一压力高的第二压力从邻接止动器40和40的模板34加到第二配线板16上，以防止焊球18的剥离。模具树脂注入空腔32.版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2008135781A Production of substrate with built-in chip 有权
标题翻译：用内置芯片生产基板
公开(公告)号：JP2008135781A
公开(公告)日：2008-06-12
申请号：JP2008031917
申请日：2008-02-13
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： YAMANO KOJI , IIZUKA HAJIME , SAKAGUCHI HIDEAKI , KOBAYASHI TOSHIO , ARAI SUNAO , KOBAYASHI TAKESHI , KOYAMA TETSUYA , IIDA KIYOAKI , MASHIMA TOMOAKI , TANAKA KOICHI , KUNIMOTO YUJI , YANAGISAWA TAKASHI
IPC分类号： H05K3/46 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L21/565 , H01L24/73 , H01L25/0657 , H01L2221/68345 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06568 , H01L2924/01019 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/19106 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a substrate with a built-in chip having excellent production yield and high reliability in a multilayered wiring connected to the built-in semiconductor chip. SOLUTION: The manufacturing method has a first step for mounting a semiconductor chip onto a first substrate with a first wiring formed thereon, and a second step for sticking the first substrate to a second substrate with a second wiring formed thereon. The semiconductor chip is sealed in the second step between the first substrate and the second substrate, and the first wiring is electrically connected to the second wiring to form a multilayered wiring connecting the semiconductor chip. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有内置芯片的基板的制造方法，该内置芯片在与内置半导体芯片连接的多层布线中具有优异的生产率和高可靠性。解决方案：制造方法具有将半导体芯片安装到其上形成有第一布线的第一基板上的第一步骤，以及将第一基板粘附到第二基板上的第二步骤，其中形成有第二布线。半导体芯片在第一基板和第二基板之间的第二阶段中被密封，并且第一布线电连接到第二布线，以形成连接半导体芯片的多层布线。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2008010885A Chip built-in substrate 有权
标题翻译：芯片内置基板
公开(公告)号：JP2008010885A
公开(公告)日：2008-01-17
申请号：JP2007218182
申请日：2007-08-24
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： YAMANO KOJI , IIZUKA HAJIME , SAKAGUCHI HIDEAKI , KOBAYASHI TOSHIO , ARAI SUNAO , KOBAYASHI TAKESHI , KOYAMA TETSUYA , IIDA KIYOAKI , MASHIMA TOMOAKI , TANAKA KOICHI , KUNIMOTO YUJI , YANAGISAWA TAKASHI
IPC分类号： H01L23/12 , H01L25/10 , H01L25/11 , H01L25/18 , H05K3/46
CPC分类号： H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2225/06568 , H01L2924/01019 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/19106 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a chip built-in substrate which gives satisfactory manufacturing yield and high reliability in multilayer wirings connected with a built-in semiconductor chip. SOLUTION: The chip built-in substrate is manufactured with a first step of mounting the semiconductor chip 110 on a first substrate whereupon a first wiring is formed, and a second step of bonding a second substrate whereupon a second wiring is formed with the first substrate. In the second step, the semiconductor chip 110 is sealed between the first substrate and the second substrate, the first wiring is electrically connected with the second wiring, and the multilayer wiring connected with the semiconductor chip 110 is formed. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种内置衬底，其在与内置半导体芯片连接的多层配线中具有令人满意的制造成品率和高可靠性。解决方案：芯片内置基板的制造是将半导体芯片110安装在形成第一布线的第一基板上的第一步骤，以及形成第二布线的第二基板接合的第二步骤第一个底物。在第二步骤中，将半导体芯片110密封在第一基板和第二基板之间，第一布线与第二布线电连接，形成与半导体芯片110连接的多层布线。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007027527A Board and its manufacturing method 审中-公开
标题翻译：董事会及其制造方法
公开(公告)号：JP2007027527A
公开(公告)日：2007-02-01
申请号：JP2005209509
申请日：2005-07-20
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KOBAYASHI TOSHIO , ARAI SUNAO , MIYASHITA HITOSHI , IIZUKA HAJIME
IPC分类号： H01L23/12 , H01L25/00
摘要： PROBLEM TO BE SOLVED: To provide a board which can increase the positional accuracy of an electronic component fixed to the main body of the board and can make the board thin, and also to provide a method for manufacturing the board.
SOLUTION: The board has a body 11, a recess 21 formed on the board body 11 and nearly corresponding in size to the outer shape of a capacitor component 13, the capacitor component 13 positioned on the recess 21, and notches 22 formed in the board body 11 forming side surfaces of the recess 21.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够提高固定在基板主体上的电子部件的位置精度的板，能够使基板变薄，并且还提供一种板的制造方法。解决方案：板具有主体11，形成在板主体11上的几乎对应于电容器部件13的外形几乎相应的凹部21，位于凹部21上的电容器部件13和形成的凹口22 在板体11上形成凹部21的侧表面。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006339276A Substrate for connection and manufacturing method thereof 审中-公开
标题翻译：用于连接的基板及其制造方法
公开(公告)号：JP2006339276A
公开(公告)日：2006-12-14
申请号：JP2005159992
申请日：2005-05-31
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KOBAYASHI TOSHIO , ARAI SUNAO
IPC分类号： H05K1/18 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a substrate for connection where a plurality of chip capacitors can be arranged between one set of grounding and power source lines, and manufacturing costs can be reduced, and to provide a method of manufacturing the substrate for connection.
SOLUTION: A chip capacitor module 12 comprises first and second leads 23, 24 for connection arranged alternately; and a plurality of chip capacitors 25 that are provided between the first lead 23 for connection and the second one 24 for connection, and are electrically connected to the first and second leads 23, 24 for connection. The chip capacitor module 12 is provided at an opening 21 formed in a substrate body 11.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于连接的基板，其中可以在一组接地和电源线之间布置多个片式电容器，并且可以减少制造成本，并且提供一种制造用于连接。解决方案：片式电容器模块12包括交替布置的用于连接的第一和第二引线23,24; 以及设置在用于连接的第一引线23和用于连接的第二引线23之间的多个片状电容器25，并且电连接到用于连接的第一和第二引线23,24。芯片电容器模块12设置在形成在基板主体11中的开口21处。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2012134270A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012134270A
公开(公告)日：2012-07-12
申请号：JP2010284110
申请日：2010-12-21
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： MIKI SHOTA , YAMANO KOJI , KOBAYASHI TOSHIO
IPC分类号： H01L23/12 , H01L21/56
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/19 , H01L2224/12105 , H01L2924/01029 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which cracks and disconnection are hard to occur on a wiring pattern and a manufacturing method of the same.SOLUTION: The present semiconductor manufacturing method comprises: a first step of arranging a semiconductor chip on which an electrode pad is formed on a circuit formation surface side on one surface of a support member in such a manner that the electrode pad contacts the one surface of the support member; a second step of forming a first insulation layer on the one surface of the support member so as to cover side faces and a rear face of the semiconductor chip; a third step of removing the support member to form an internal connection terminal on the electrode pad; a fourth step of forming a second insulation layer on the circuit formation surface of the semiconductor chip and the first insulation layer so as to cover the internal connection terminal; a fifth step of exposing an end part of the internal connection terminal on a top face of the second insulation layer; and a sixth step of forming a wiring pattern electrically connected with the end part of the internal connection terminal on the top face of the second insulation layer.
摘要翻译：要解决的问题：提供一种在布线图案上难以发生裂纹和断开的半导体器件及其制造方法。解决方案：本半导体制造方法包括：第一步骤，以使得电极焊盘接触电极焊盘的方式，在支撑部件的一个表面上的电路形成表面侧上布置形成有电极焊盘的半导体芯片支撑构件的一个表面; 在支撑部件的一个表面上形成第一绝缘层以覆盖半导体芯片的侧面和背面的第二步骤; 去除所述支撑构件以在所述电极焊盘上形成内部连接端子的第三步骤; 在所述半导体芯片的电路形成面和所述第一绝缘层上形成覆盖所述内部连接端子的第二绝缘层的第四工序; 将内部连接端子的端部暴露在第二绝缘层的顶面上的第五步骤; 以及在第二绝缘层的顶面上形成与内部连接端子的端部电连接的布线图案的第六步骤。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2010109180A Method of manufacturing substrate with built-in semiconductor device 有权
标题翻译：用内置半导体器件制造衬底的方法
公开(公告)号：JP2010109180A
公开(公告)日：2010-05-13
申请号：JP2008280169
申请日：2008-10-30
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KOBAYASHI TOSHIO , ARAI SUNAO , YAMANO KOJI
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/96 , H01L24/97 , H01L2224/02333 , H01L2224/12105 , H01L2224/13022 , H01L2224/16 , H01L2224/24226 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2224/82
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a substrate with a built-in semiconductor device for suppressing the raise of a manufacturing cost, and achieving microfabrication. SOLUTION: The method is required to include: a first step of preparing a semiconductor device having a semiconductor integrated circuit 10, a connection terminal 12, and the first insulating layer 13; a second step of arranging the semiconductor device 10 on the surface of a support; a third step of forming the second insulating layer 41, so as to embed at least the side surfaces of the semiconductor device 10; a fourth step of removing the support; a fifth step of forming the third insulating layer 42 on the opposite surface; a sixth step of preparing a wiring board with the first wiring pattern, and performing fixing onto surfaces on the opposite side of an exposure part in the semiconductor device 10 and the second insulating layer 41; a seventh step of forming a via-hole 41X to expose the first wiring pattern; and an eighth step of forming the second wiring pattern for electrically connecting the exposure part to the first wiring pattern via the via-hole. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于抑制制造成本提高的内置半导体装置的基板的制造方法，并且实现微细加工。解决方案：该方法需要包括：制备具有半导体集成电路10，连接端子12和第一绝缘层13的半导体器件的第一步骤; 将半导体器件10布置在支撑体的表面上的第二步骤; 形成第二绝缘层41的第三步骤，以便至少嵌入半导体器件10的侧表面; 移除支架的第四步骤; 在相对的表面上形成第三绝缘层42的第五步骤; 制备具有第一布线图案的布线板并且在半导体器件10和第二绝缘层41中的曝光部分的相对侧上的表面上进行固定的第六步骤; 形成通孔41X以暴露第一布线图案的第七步骤; 以及形成用于经由通孔将曝光部分电连接到第一布线图案的第二布线图案的第八步骤。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2010073893A Semiconductor device and production process thereof 有权
标题翻译：半导体器件及其生产工艺
公开(公告)号：JP2010073893A
公开(公告)日：2010-04-02
申请号：JP2008239751
申请日：2008-09-18
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： ARAI SUNAO , KOBAYASHI TOSHIO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , H01L21/568 , H01L2224/12105 , H01L2224/19 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can fully meet the requirement even when the number of external connection terminals needs to be increased due to high packaging and to provide a production process thereof. SOLUTION: A semiconductor device 10 includes chips 30, 32 which are laminated in a face-down and face-up mode respectively to an opening OP of a lead frame 20. An electrode pad 33 of the chip 32 is connected to a lead 22 through a wire 34. Furthermore, a laminated wiring layer 40 having the chip 30 and the lead frame 20 mounted on one of the sides and a sealing resin layer 50 which seals the chips 30 and 32, the lead frame 20, or the like are also included. The wiring pattern drawn from the electrode pad 31 and lead 22 of the chip 30 is electrically connected to a pad 44P which is arranged at the other side of the laminated wiring layer 40. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供即使当由于高包装需要增加外部连接端子的数量而能够完全满足要求并提供其制造方法的半导体装置。解决方案：半导体器件10包括分别以引脚框架20的开口OP面对面和朝上模式层叠的芯片30,32。芯片32的电极焊盘33连接到另外，具有安装在其一侧的芯片30和引线框架20的层叠布线层40和密封芯片30,32的密封树脂层50，引线框20或者喜欢也包括在内。从芯片30的电极焊盘31和引线22引出的布线图案电连接到布置在层叠布线层40的另一侧的焊盘44P。（C）2010，JPO＆INPIT

10. 发明专利

JP2009272512A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009272512A
公开(公告)日：2009-11-19
申请号：JP2008122998
申请日：2008-05-09
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KOBAYASHI TOSHIO , ARAI SUNAO , IIZUKA HAJIME
IPC分类号： H01L23/12
CPC分类号： H01L21/568 , H01L2224/04105 , H01L2224/12105
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for bonding (laminating) a semiconductor chip to an insulating layer by using the adhesive power of an insulating layer in providing a semiconductor embedded between insulators. SOLUTION: The method of manufacturing the semiconductor device includes: a step of forming, on the surface of a metallic layer 10 formed on one side of a support 12, a hole 18 for connecting to an electrode pad 32 of a semiconductor element 30; a step of laminating a non-cured insulating layer 20 on the surface of the metallic layer 10; a step of aligning the position of the electrode pad 32 to the position of the hole 18 formed in the metallic layer 10, and for loading the semiconductor element 30 on the insulating layer 20; a step of curing the insulating film 20; a step of removing a support 12; a step of removing the insulating film 20 at the position of the hole 18 formed in the metallic layer 10, and for forming a via hole 36 from which the electrode pad 32 is exposed; and a step of resin-sealing the loaded side face of the semiconductor element 30. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，所述半导体器件通过在提供绝缘体中嵌入的半导体中使用绝缘层的粘合力将半导体芯片接合（层合）到绝缘层。解决方案：制造半导体器件的方法包括：在形成在支撑体12的一侧的金属层10的表面上形成用于连接到半导体元件的电极焊盘32的孔18的步骤 30; 将非固化绝缘层20层压在金属层10的表面上的步骤; 将电极焊盘32的位置与形成在金属层10中的孔18的位置对准并将半导体元件30装载在绝缘层20上的步骤; 固化绝缘膜20的步骤; 去除支撑件12的步骤; 在形成在金属层10中的孔18的位置处去除绝缘膜20并形成电极焊盘32从其露出的通孔36的步骤; 以及树脂密封半导体元件30的负载侧面的步骤。版权所有（C）2010，JPO＆INPIT

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