专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2005167056A Thin film transistor and its manufacturing method 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：JP2005167056A
公开(公告)日：2005-06-23
申请号：JP2003405620
申请日：2003-12-04
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： ARAO TATSUYA , HIGAKI KINSEI , KITAKADO HIDETO , MATSUO TAKUYA
IPC分类号： H01L21/20 , H01L21/265 , H01L21/322 , H01L21/336 , H01L29/786
CPC分类号： H01L29/78621 , H01L27/1277 , H01L2029/7863
摘要： PROBLEM TO BE SOLVED: To avoid OFF current failure caused by segregation of nickel as a crystallization catalyst element in a thin film transistor. SOLUTION: An outer edge part of a gate electrode is spaced at least about 0.5 μm apart from a source-drain region or the like wherein phosphorus as a gettering element is implanted for preventing segregation of nickel in an area near an outer edge part of the gate electrode. This is realized by controlling the position of phosphorus implantation and by reducing right and left sizes of the gate electrode. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了避免在薄膜晶体管中作为结晶催化剂元素的镍偏析引起的电流故障。解决方案：栅电极的外边缘部分与源极 - 漏极区域等间隔开至少约0.5μm，其中作为吸杂元素的磷被植入以防止镍在外边缘附近的区域偏析部分栅电极。这是通过控制磷注入的位置和减小栅电极的左右尺寸来实现的。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005183774A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005183774A
公开(公告)日：2005-07-07
申请号：JP2003424370
申请日：2003-12-22
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： ARAO TATSUYA , KITAKADO HIDETO , MATSUO TAKUYA , KIYOUHO MASANORI
IPC分类号： H01L27/08 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents spot-facing in an underlayer insulating film under a semiconductor layer. SOLUTION: In the manufacturing method of the semiconductor device, semiconductor layers 3a, 3b are formed on the underlayer insulating film 2, a first insulating film 4 is formed on the semiconductor layers 3a, 3b, and the first insulating film 4 located on a channel formation region of the semiconductor layer 3a at a low voltage driving side is removed by etching using the semiconductor layer 3a as an etching stopper. Consequently, a second insulating film 6 is formed on the channel formation region of the semiconductor layer 3a and the first insulating film 4 with the first insulating film 4 left on a source region and a drain region of the semiconductor layer 3a and the semiconductor layer 3b. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种防止在半导体层下面的下层绝缘膜中的点对准的半导体器件。解决方案：在半导体器件的制造方法中，半导体层3a，3b形成在下层绝缘膜2上，第一绝缘膜4形成在半导体层3a，3b上，第一绝缘膜4位于在半导体层3a的低电压驱动侧的沟道形成区域上通过使用半导体层3a作为蚀刻停止层的蚀刻来去除。因此，第二绝缘膜6形成在半导体层3a和第一绝缘膜4的沟道形成区上，第一绝缘膜4留在半导体层3a和半导体层3b的源极区域和漏极区域上。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005210109A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005210109A
公开(公告)日：2005-08-04
申请号：JP2004374153
申请日：2004-12-24
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： ONUMA HIDETO , SAKAKURA MASAYUKI , MITANI YASUHIRO , MATSUO TAKUYA , KITAKADO HIDETO
IPC分类号： H01L21/20 , H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which suppresses the growth of pores in a crystalline semiconductor film.
SOLUTION: The semiconductor device manufacturing method comprises a step of forming an amorphous silicon film 3 on a substrate 1 having an insulation surface, adding a metal element such as Ni onto the amorphous silicon film 3 for accelerating the crystallization of the amorphous silicon film, heat treating the amorphous silicon film 3 to crystallize this film, thus forming a crystalline silicon film 5 on the substrate, removing a silicon oxide film formed by the heat treatment on the crystalline silicon film 5 surface with a solution containing organic solvents and a fluoride, and irradiating the crystalline silicon film 5 with a laser beam or a strong light beam.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供抑制结晶半导体膜中的孔的生长的半导体器件及其制造方法。解决方案：半导体器件制造方法包括在具有绝缘表面的衬底1上形成非晶硅膜3的步骤，在非晶硅膜3上添加诸如Ni的金属元素以加速非晶硅的结晶化膜，热处理非晶硅膜3以使该膜结晶，从而在基板上形成结晶硅膜5，通过含有有机溶剂的溶液和在结晶硅膜5表面上除去通过热处理形成的氧化硅膜，并且用激光束或强光束照射结晶硅膜5。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005191212A Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005191212A
公开(公告)日：2005-07-14
申请号：JP2003429510
申请日：2003-12-25
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： FUJIKAWA SAISHI , SATO TOMOHIKO , SASAGAWA SHINYA , MATSUO TAKUYA , KITAKADO HIDETO
IPC分类号： H01L29/423 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/41 , H01L29/49 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method therefor, in which generation of damage or contamination of semiconductor layer can be controlled, even when gate insulating films are formed into different thicknesses. SOLUTION: The semiconductor device is manufactured by forming semiconductor layers 3a, 3b on a substrate, forming first insulating films 4, respectively on the semiconductor layers 3a, 3b, forming a second insulating film 5 on the semiconductor layer 3b via the first insulating film 4, and forming a third insulating film 6 on the second insulating film 5. The first insulating film 4, formed on the semiconductor layer 3a, forms a first gate insulating film, and the first to third insulating films 4 to 6 formed on the semiconductor layer 3b form a second gate insulating film. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使当栅极绝缘膜形成为不同的厚度时，提供可以控制半导体层的损伤或污染的产生的半导体器件及其制造方法。解决方案：半导体器件通过在衬底上形成半导体层3a，3b来制造，分别在半导体层3a，3b上形成第一绝缘膜4，在半导体层3b上形成第二绝缘膜5，经由第一绝缘膜4，并且在第二绝缘膜5上形成第三绝缘膜6.形成在半导体层3a上的第一绝缘膜4形成第一栅极绝缘膜，形成在第一绝缘膜4上的第一至第三绝缘膜4至6 半导体层3b形成第二栅极绝缘膜。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005183773A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005183773A
公开(公告)日：2005-07-07
申请号：JP2003424364
申请日：2003-12-22
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： FUJIKAWA SAISHI , ASANO ETSUKO , ARAO TATSUYA , YOKOSHIMA TAKASHI , MATSUO TAKUYA , KITAKADO HIDETO
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can simplify a process by doping impurities at once, and to provide its manufacturing method.
SOLUTION: In the manufacturing method of the semiconductor device, semiconductor layers 3a, 3b are formed on a substrate 1; a first insulating film 4 is formed on the semiconductor layer; first and second conductive films 5a, 6b are formed thereon; a first gate electrode 8 consisting of the first and second conductive films is formed on the semiconductor film 3a via the first insulating film, so that a part of the first conductive film 5a is exposed from the second conductive film 6b; a second insulating layer 9 is formed on the first insulating film; third and fourth conductive films 10a, 11b are formed thereon; and a second gate electrode 13 consisting of the third and fourth conductive films and formed so that a part of the third conductive film 10a is exposed from the fourth conductive film 11b is formed on the semiconductor layer 3b via the first and second insulating films.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种通过一次掺杂杂质来简化工艺的半导体器件，并提供其制造方法。解决方案：在半导体器件的制造方法中，半导体层3a，3b形成在基板1上; 在半导体层上形成第一绝缘膜4; 在其上形成第一和第二导电膜5a，6b; 通过第一绝缘膜在半导体膜3a上形成由第一导电膜和第二导电膜构成的第一栅电极8，使第一导电膜5a的一部分从第二导电膜6b露出; 在第一绝缘膜上形成第二绝缘层9; 在其上形成第三和第四导电膜10a，11b; 以及由第三导体膜和第四导电膜构成的第二栅电极13，其通过第一绝缘膜和第二绝缘膜形成在半导体层3b上，从第四导电膜11b露出第三导电膜10a的一部分。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005167057A High on-property thin film transistor and its manufacturing method 有权
标题翻译：高性能薄膜晶体管及其制造方法
公开(公告)号：JP2005167057A
公开(公告)日：2005-06-23
申请号：JP2003405622
申请日：2003-12-04
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： ASANO ETSUKO , ARAO TATSUYA , MATSUO TAKUYA , KIYOUHO MASANORI , KITAKADO HIDETO
IPC分类号： H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To avoid hot carrier deterioration in a thin film transistor having an LDD structure or a GOLD structure.
SOLUTION: Doping to an LDD is made slightly high dose/high acceleration. An upper side layer which is subjected to doping of relatively low concentration and a lower side layer which is subjected to doping of relatively high concentration are formed for avoiding hot carrier deterioration and also avoiding an increase of ON resistance.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了避免具有LDD结构或GOLD结构的薄膜晶体管的热载流子劣化。
解决方案：对LDD的掺杂量略高，剂量/高加速度。形成经受相对低浓度掺杂的上侧层和经受相对高浓度掺杂的下侧层，以避免热载流子劣化，并且还避免了导通电阻的增加。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005123360A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005123360A
公开(公告)日：2005-05-12
申请号：JP2003355882
申请日：2003-10-16
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： ARAO TATSUYA , NODA GOJI , MATSUO TAKUYA , KITAKADO HIDETO , KIYOUHO MASANORI
IPC分类号： G02F1/1343 , G02F1/1368 , H01L21/20 , H01L21/28 , H01L21/336 , H01L21/77 , H01L21/86 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/786
CPC分类号： H01L29/78621 , H01L27/1214 , H01L29/6675 , H01L29/78648
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can be reduced in manufacturing cost by reducing the number of masks, and also to provide its manufacturing method. SOLUTION: In manufacturing the semiconductor device, a semiconductor layer 3 including a source and a drain regions 10 and 11 and LDD regions 16 and 17, a gate insulation film 5, and a gate electrode 6 are formed, and a first and a second interlayer insulation films 24 and 25 are formed thereon. In the interlayer insulation films, contact holes 25a and 25c which are positioned above the source and drain regions respectively and an opening 25b which is positioned above the gate electrode and the LDD regions are formed. Within the opening, a second gate electrode 26b consisting of a transparent conductive film is so formed as to cover the gate electrode and the LDD regions, and a pixel electrode 26a is formed on the second interlayer insulation film. Then, the gate insulation film inside the contact holes is removed, and interconnections 27 and 28 connected to the source and drain regions respectively are formed. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供通过减少掩模的数量可以降低制造成本的半导体器件，并且还提供其制造方法。解决方案：在制造半导体器件时，形成包括源极和漏极区域10和11以及LDD区域16和17的半导体层3，栅极绝缘膜5和栅极电极6，并且第一和在其上形成第二层间绝缘膜24和25。在层间绝缘膜中，分别形成位于源极和漏极区之上的接触孔25a和25c以及位于栅电极和LDD区之上的开口25b。在开口内，由透明导电膜构成的第二栅电极26b形成为覆盖栅电极和LDD区，并且在第二层间绝缘膜上形成像素电极26a。然后，去除接触孔内部的栅极绝缘膜，并分别连接到源区和漏极区的互连27和28。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005165157A Active matrix type liquid crystal display panel and its defective pixel discrimination method, and element substrate for active matrix type liquid crystal display panel and its defective element discrimination method 有权
标题翻译：主动矩阵型液晶显示面板及其有缺陷的像素辨识方法及主动矩阵式液晶显示面板的元件基板及其有缺陷的元件辨识方法
公开(公告)号：JP2005165157A
公开(公告)日：2005-06-23
申请号：JP2003406660
申请日：2003-12-05
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： HAYAKAWA MASAHIKO , SHIONOIRI YUTAKA , ATAMI TOMOAKI , KITAKADO HIDETO , MATSUO TAKUYA
IPC分类号： G02F1/13 , G02F1/133 , G02F1/1368 , G09G3/20 , G09G3/36 , H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display panel with which presence/no presence of a pixel defect can be discriminated without using an expensive and large-scale evaluation device and an efficient aging test can be performed. SOLUTION: A pixel capacitance element 104 for evaluation and a differential amplifying circuit 105 are provided to a liquid crystal cell which constitutes one pixel. When a pixel TFT 103 for switching is turned on and the charged pixel capacitance element 104 for evaluation has an appropriate charge holding function, when the differential amplifying circuit 105 operates, since voltage of a first input is higher than the voltage of a second input wherein a defect discrimination criterion signal 106 is inputted, the level of output of the differential amplifying circuit 105 is made high, and a pixel capacitance element 107 for display is charged and a liquid crystal 108 is displayed. When the pixel capacitance element 104 for evaluation does not have the appropriate charge holding function, when the differential amplifying circuit 105 operates, the level of its output is made low, the pixel capacitance element 107 for display is not charged and the liquid crystal 108 is not displayed. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种有源矩阵型液晶显示面板，可以在不使用昂贵且大规模的评估装置的情况下进行区分像素缺陷的存在/不存在，并且可以进行有效的老化测试。解决方案：用于评估的像素电容元件104和差分放大电路105被提供给构成一个像素的液晶单元。当用于切换的像素TFT103导通，并且用于评估的带电像素电容元件104具有适当的电荷保持功能时，当差分放大电路105工作时，由于第一输入的电压高于第二输入的电压，输入缺陷判别基准信号106，使差分放大电路105的输出电平为高电平，对显示用的像素电容元件107进行充电，并显示液晶108。当用于评估的像素电容元件104不具有适当的电荷保持功能时，当差分放大电路105工作时，其输出电平变低，用于显示的像素电容元件107不被充电，液晶108为不显示。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005093871A Semiconductor device and manufacturing method 有权
标题翻译：半导体器件和制造方法
公开(公告)号：JP2005093871A
公开(公告)日：2005-04-07
申请号：JP2003327729
申请日：2003-09-19
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： NODA GOJI , KITAKADO HIDETO , MATSUO TAKUYA
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66757 , H01L29/42384 , H01L29/78603 , H01L29/78621 , H01L29/78675
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can improve the effect of hydrogenating treatment even when a gold structure is used, and to provide a method of manufacturing the device.
SOLUTION: In the method of manufacturing the semiconductor device, the crystal defect section of a semiconductor layer 3 is hydrogen-terminated by forming a gate insulating film 5 on the semiconductor layer 3, source and drain regions 10 and 11 and LDD regions 15 and 16 in the semiconductor layer 3, a main gate 7 on the gate insulating film 5, a sub-gate 4 on the main gate 7 and gate insulating film 5 to cover part of the main gate 7 and surface of the LDD region of either the source region 10 or drain region 11, and a hydrogen-containing interlayer insulating film 6 on the sub-gate 4, main gate 7, and gate insulating film 5 and performing heat treatment for hydrogenation.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供即使在使用金结构时也可以提高氢化处理的效果的半导体器件，并提供制造该器件的方法。解决方案：在制造半导体器件的方法中，通过在半导体层3，源极和漏极区域10和11以及LDD区域上形成栅极绝缘膜5，半导体层3的晶体缺陷部分被氢端接半导体层3中的15和16，栅极绝缘膜5上的主栅极7，主栅极7上的子栅极4和用于覆盖主栅极7的一部分和主栅极7的LDD区域的表面的栅极绝缘膜5 源极区域10或漏极区域11，以及子栅极4，主栅极7和栅极绝缘膜5上的含氢层间绝缘膜6，并进行氢化加热处理。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005093870A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005093870A
公开(公告)日：2005-04-07
申请号：JP2003327725
申请日：2003-09-19
申请人： Semiconductor Energy Lab Co Ltd , Sharp Corp , シャープ株式会社 , 株式会社半導体エネルギー研究所
发明人： NODA GOJI , KITAKADO HIDETO
IPC分类号： G02F1/1368 , H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can be improved in the withstand voltage between a source and drain or hot-carrier resistance, and to provide a method of manufacturing the device. SOLUTION: The semiconductor device is provided with a gate insulating film 5 formed on semiconductor layers 3 and 4, a gate electrode 7 formed on the gate insulating film 5 and having a hat-like shape formed by exposing part of a first conductive film from a second conductor film, and first LDD regions 21 and 22 formed in the semiconductor layer under the first conductive film exposed from the second conductive film of the gate electrode 7. The device is also provided with second LDD regions 15 and 16 formed in the semiconductor layer positioned on the outside of the first LDD regions and are higher in impurity concentration than the regions, source and drain regions 10 and 11 formed in the semiconductor layer positioned on the outside of the second LDD regions, and an auxiliary gate which is disposed to cover the surface of the gate electrode 7, at least, the first and second LDD regions on the drain region side. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以提高源极和漏极或热载流子电阻之间的耐受电压的半导体器件，并提供制造器件的方法。解决方案：半导体器件设置有形成在半导体层3和4上的栅极绝缘膜5，形成在栅极绝缘膜5上并具有帽状形状的栅电极7，其形成为通过暴露部分第一导电由第二导体膜形成的第一LDD区域21和第二LDD区域21和22形成在从栅电极7的第二导电膜暴露的第一导电膜下面的半导体层中。该器件还设置有第二LDD区域15和16，半导体层位于第一LDD区域的外侧，并且杂质浓度高于形成在位于第二LDD区域的外部的半导体层中的区域，源极和漏极区域10和11，以及辅助栅极设置成覆盖栅极电极7的表面，至少覆盖漏极区域侧的第一和第二LDD区域。版权所有（C）2005，JPO＆NCIPI

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式