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1. 发明专利

JP2012004500A Mos type semiconductor device for protection against static electricity 有权
标题翻译：用于保护静电的MOS型半导体器件
公开(公告)号：JP2012004500A
公开(公告)日：2012-01-05
申请号：JP2010140893
申请日：2010-06-21
申请人： Seiko Instruments Inc , セイコーインスツル株式会社
发明人： SHIMAZAKI KOICHI , RISAKI TOMOMITSU
IPC分类号： H01L27/06 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a MOS type semiconductor device capable of improving the ESD resistance of an ESD element.SOLUTION: In an ESD element 21, a plurality of gate electrodes 3 extending in one direction are parallel to each other on a p-type well region 2 formed on a surface of a semiconductor substrate 1 via a gate insulating film, just under the areas of gate electrodes 3 on a surface of the p-type well region 2 are channel regions 9. Regions between channel regions 9 are N+ source regions 5 or N+ drain regions 4, N+ source regions 5 and N+ drain regions 4 are alternately arranged. Gate electrode junction regions 10 are provided so as to divide N+ drain region 4 between adjacent gate electrodes 3 parallelly arranged and connect adjacent gate electrodes 3 each other. Regions 11 having an impurity concentration equal to that of channel regions 9 are provided in just under the areas of gate electrode junction regions 10.
摘要翻译：解决的问题：提供能够提高ESD元件的ESD电阻的MOS型半导体器件。解决方案：在ESD元件21中，在一个方向上延伸的多个栅电极3通过栅极绝缘膜在形成在半导体衬底1的表面上的p型阱区2上彼此平行，只是在p型阱区2的表面上的栅电极3的区域是沟道区9.沟道区9之间的区域是N +源极区5或N +漏极区4，N +源极区5和N +漏极区4交替安排。栅电极接合区域10被设置成在相邻的栅极电极3之间划分N +漏极区域4并排布置，并且相邻的栅极电极3彼此连接。杂质浓度等于沟道区域9的区域11设置在栅电极接合区域10的正下方。版权所有：（C）2012，JPO＆INPIT

2. 发明专利

JP2010177434A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010177434A
公开(公告)日：2010-08-12
申请号：JP2009018251
申请日：2009-01-29
申请人： Seiko Instruments Inc , セイコーインスツル株式会社
发明人： RISAKI TOMOMITSU , NAKANISHI AKISHIGE , SHIMAZAKI KOICHI
IPC分类号： H01L21/822 , H01L21/331 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/088 , H01L29/73 , H01L29/78
CPC分类号： H01L23/62 , H01L27/0259 , H01L27/027 , H01L29/0821 , H01L29/0847 , H01L29/402 , H01L29/423 , H01L29/735 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with high ESD resistance. SOLUTION: A semiconductor layer includes a PW layer 24 having higher impurity concentration than that of a semiconductor substrate provided on the surface of a semiconductor substrate, an NW layer 23 having higher impurity concentration than that of the semiconductor substrate provided in contact with the PW layer 24 on the surface of the semiconductor substrate, a p+ base layer 5 having higher impurity concentration than that of the PW layer 24 provided on the surface of a semiconductor substrate in the PW layer 24, an n+ collector layer 2 having higher impurity concentration than that of the NW layer provided on the surface of a semiconductor substrate in the NW layer 23, an n+ emitter layer 6 having higher impurity concentration than that of the PW layer 24 positioned between the p+ base layer 5 and the n+ collector layer 2 and provided on the surface of the semiconductor substrate in the PW layer 24, and an n± layer 10 having lower impurity concentration than that of the n+ collector layer 2 and higher impurity concentration than that of the NW layer 23 provided in contact with the n+ collector layer 2 between the n+ collector layer 2 and the PW layer 24. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供具有高ESD电阻的半导体器件。解决方案：半导体层包括具有比设置在半导体衬底表面上的半导体衬底的杂质浓度高的杂质浓度的PW层24，杂质浓度高于与所述半导体衬底接触的半导体衬底的杂质浓度高的NW层23 在半导体衬底的表面上的PW层24，具有比在PW层24中的半导体衬底的表面上设置的PW层24的杂质浓度高的p +基底层5，具有较高杂质的n +集电极层2 浓度比在NW层23中的半导体衬底的表面上设置的NW层的浓度高，杂质浓度高于位于p +基极层5和n +集电极层2之间的PW层24的杂质浓度的n +发射极层6 并且设置在PW层24中的半导体衬底的表面上，并且具有比n + col的杂质浓度低的n±10层导电层2和杂质浓度高于在n +集电极层2和PW层24之间与n +集电极层2接触的NW层23的杂质浓度。（C）2010，JPO＆INPIT

3. 发明专利

JP2008292182A Hall sensor 审中-公开
标题翻译：霍尔传感器
公开(公告)号：JP2008292182A
公开(公告)日：2008-12-04
申请号：JP2007135418
申请日：2007-05-22
申请人： Seiko Instruments Inc , セイコーインスツル株式会社
发明人： SHIMAZAKI KOICHI , TAKASU HIROAKI
IPC分类号： G01R33/07 , G01R33/02 , H01L43/04
摘要： PROBLEM TO BE SOLVED: To prevent performance deterioration of a hall element by decreasing a stress applied from a resin used for a package to the hall element by packaging the package of the hall sensor through an air gap without closely attaching it to the hall element.
SOLUTION: Without closely attaching a hall element arranged on an insulating supporting substrate to a plastic resin, a package is formed by molding the plastic resin through an air gap so that applied force from the plastic resin to the hall element is decreased to prevent performance deterioration of the hall element. With reduced contact area between the insulating supporting substrate and the hall element, an influence of the stress is decreased furthermore.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了通过将通过空气间隙包装霍尔传感器的包装而不用紧密地附接到霍尔元件的方式来减小从用于包装的树脂施加到霍尔元件的树脂的应力来防止霍尔元件的性能劣化大厅元素解决方案：在将绝缘支撑基板上布置的霍尔元件紧密地连接到塑料树脂上的情况下，通过气隙模塑塑料树脂形成封装，使得从塑料树脂到霍尔元件的施加力降低到防止霍尔元件的性能恶化。由于绝缘支撑基板与霍尔元件之间的接触面积减小，因此应力的影响进一步降低。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2014003097A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014003097A
公开(公告)日：2014-01-09
申请号：JP2012136288
申请日：2012-06-15
申请人： Seiko Instruments Inc , セイコーインスツル株式会社
发明人： RISAKI TOMOMITSU , NAKANISHI AKISHIGE , SAKURAI HITOMI , SHIMAZAKI KOICHI
IPC分类号： H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522
CPC分类号： H01L24/45 , H01L23/522 , H01L23/5226 , H01L23/60 , H01L24/05 , H01L24/48 , H01L24/78 , H01L24/85 , H01L27/0296 , H01L2224/02166 , H01L2224/04042 , H01L2224/05011 , H01L2224/05013 , H01L2224/05014 , H01L2224/05085 , H01L2224/05095 , H01L2224/05096 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/45144 , H01L2224/48451 , H01L2224/48463 , H01L2224/78301 , H01L2224/78303 , H01L2224/85181 , H01L2224/85205 , H01L2924/00014 , H01L2924/35 , H01L2224/05599 , H01L2224/05099 , H01L2924/00015
摘要： PROBLEM TO BE SOLVED: To inhibit cracks under a pad opening and increase in chip size.SOLUTION: A semiconductor device comprises: a protection film 6 having a pad opening 9 which exposes a part of an uppermost metal film 3 and in which the pad opening 9 is rectangular in a square shape and an opening width is denoted by d0; and a second metal film 2 having an opening under the pad opening 9 in which the opening is rectangular in a square shape and an opening width is denoted by d4. A distance between an opening edge of the protection film 6 and an opening edge of the second metal film 2 is denoted by d3. That is, the second metal film 2 has a rectangular ring shape and protrudes inside the pad opening 9 by the distance d3.
摘要翻译：要解决的问题：抑制焊盘开口处的裂纹并增加芯片尺寸。解决方案：半导体器件包括：保护膜6，其具有暴露部分最上面金属膜3的焊盘开口9，其中焊盘开口 9是矩形的方形，开口宽度由d0表示; 以及第二金属膜2，其具有在垫片开口9的下方的开口，其中开口为矩形的正方形，开口宽度由d4表示。保护膜6的开口边缘与第二金属膜2的开口边缘之间的距离由d3表示。也就是说，第二金属膜2具有矩形环形并且在焊盘开口9的内部突出距离d3。

5. 发明专利

JP2014138146A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014138146A
公开(公告)日：2014-07-28
申请号：JP2013007153
申请日：2013-01-18
申请人： Seiko Instruments Inc , セイコーインスツル株式会社
发明人： SHIMAZAKI KOICHI , HIROSE HIROTANE
IPC分类号： H01L27/06 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088
CPC分类号： H01L27/0266 , H01L27/0207 , H01L27/0277 , H01L27/0292 , H01L29/41758 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with high ESD resistance.SOLUTION: A plurality of source wirings 22 are formed of metal films with same shapes, respectively, and electrically and respectively connect a plurality of sources 12 to ground voltage wirings 22a. A plurality of drain wirings 23 are formed of metal films with same shapes, respectively, and electrically and respectively connect a plurality of drains 12 to input voltage wirings 23a. A plurality of gate wirings 21 are formed of metal films with same shapes, respectively, and electrically and respectively connect a plurality of gates 11 to ground voltage wirings 22a. A back gate wiring 24 is formed of a metal film with same shape, and electrically connects a back gate 14 to a ground voltage wiring 22a. The back gate wiring 24 is separated from the source wiring 22 on the source 12.
摘要翻译：要解决的问题：提供具有高ESD电阻的半导体器件。解决方案：多个源极布线22分别由具有相同形状的金属膜形成，并且将多个源极12分别连接到接地电压布线22a。多个漏极布线23分别由具有相同形状的金属膜形成，并且将多个漏极12电连接并分别连接到输入电压布线23a。多个栅极布线21分别由具有相同形状的金属膜形成，并且将多个栅极11电连接并分别连接到接地电压布线22a。背栅布线24由具有相同形状的金属膜形成，并且将背栅极14电连接到接地电压布线22a。背栅布线24与源极12上的源极布线22分离。

6. 发明专利

JP2014138145A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014138145A
公开(公告)日：2014-07-28
申请号：JP2013007152
申请日：2013-01-18
申请人： Seiko Instruments Inc , セイコーインスツル株式会社
发明人： SHIMAZAKI KOICHI , HIROSE HIROTANE
IPC分类号： H01L27/04 , H01L21/822 , H01L27/06
CPC分类号： H01L27/0266 , H01L23/535 , H01L27/0207 , H01L27/0277 , H01L29/41758 , H01L29/4238 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with high ESD resistance.SOLUTION: A ground voltage wiring 22a is electrically connected to a wiring 22b from a ground voltage pad for an external connection at one edge in its wiring direction. An input voltage wiring 23a is electrically connected to a wiring 23a from an input voltage pad for the external connection at one edge in its wiring direction. One edge of the ground voltage wiring 22a and one edge of the input voltage wiring 23a are substantively faced each other by using a center of a NMOS transistor 10 as a center.
摘要翻译：要解决的问题：提供具有高ESD电阻的半导体器件。解决方案：接地电压布线22a在布线方向上的一个边缘处从用于外部连接的接地电压焊盘电连接到布线22b。输入电压布线23a从布线方向的一个边缘处的外部连接用输入电压焊盘电连接到布线23a。接地电压布线22a的一个边缘和输入电压布线23a的一个边缘通过以NMOS晶体管10的中心为中心实质上相互面对。

7. 发明专利

JP2011192846A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011192846A
公开(公告)日：2011-09-29
申请号：JP2010058449
申请日：2010-03-15
申请人： Seiko Instruments Inc , セイコーインスツル株式会社
发明人： RISAKI TOMOMITSU , NAKANISHI AKISHIGE , SHIMAZAKI KOICHI
IPC分类号： H01L21/301 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L27/04
CPC分类号： H01L23/293 , H01L21/78 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device suitable for preventing the peeling of a film accompanying dicing and preventing abnormal discharge.
SOLUTION: A semiconductor device is formed of a scribe region 003 and an IC region 004. At least one isolation groove 007 is provided on an interlayer insulating film 002 of the scribe region 003. A sidewall 011 formed of a plug metal film is formed on side walls of both sides of the isolation groove 007. A passivation film covering at least the side walls is provided.
COPYRIGHT: (C)2011,JPO&INPIT

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