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1. 发明专利

JP2013058726A Mounting substrate and circuit device using the same 审中-公开
标题翻译：使用该安装基板和电路装置
公开(公告)号：JP2013058726A
公开(公告)日：2013-03-28
申请号：JP2012073467
申请日：2012-03-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KATO ATSUSHI , NARUSE TOSHIMICHI , IGARASHI YUUSUKE
IPC分类号： H01L23/12 , H01L25/07 , H01L25/18 , H05K1/11
CPC分类号： H05K1/0213 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H05K1/0265 , H05K1/141 , H05K3/427 , H05K2203/049 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a mounting substrate which does not complicate steps and is capable of achieving fine patterning even if conductive patterns for high current and low current are formed, and a circuit device using the same.SOLUTION: A mounting substrate comprises: a core layer 52 composed of an insulating resin; a first conductive pattern 53 provided on a surface side of the core layer 52; a second conductive pattern 54 provided on a rear side of the core layer 52; and a Via 72 provided between a first electrode 64 for high current in the first conductive pattern 53 and an external electrode 73 of the second conductor pattern 54 provided so as to correspond to the first electrode 64. The first conductive pattern 53 and the second conductive pattern 54 have the same film thickness, and a resistance value of the Via 72 is lowered so that high current flows in the external electrode 73 via the Via 72.
摘要翻译：要解决的问题：提供一种即使形成用于高电流和低电流的导电图案也能够使步骤复杂化并且能够实现精细图案化的安装基板，以及使用该安装基板的电路装置。解决方案：安装基板包括：由绝缘树脂构成的芯层52; 设置在芯层52的表面侧的第一导电图案53; 设置在芯层52的后侧的第二导电图案54; 以及设置在第一导电图案53中的高电流用的第一电极64和与第一电极64对应地设置的第二导体图案54的外部电极73之间的通孔72.第一导电图案53和第二导电图案54具有相同的膜厚度，并且Via 72的电阻值降低，使得高电流通过Via 72在外部电极73中流动。版权所有：（C）2013，JPO＆INPIT

2. 发明专利

JP2005026364A Hybrid integrated circuit 审中-公开
标题翻译：混合集成电路
公开(公告)号：JP2005026364A
公开(公告)日：2005-01-27
申请号：JP2003188523
申请日：2003-06-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NARUSE TOSHIMICHI , TAKAKUSAKI YOSHIHISA , KOBAYASHI HAJIME
IPC分类号： H05K3/28 , H01L21/48 , H01L21/68 , H01L23/13 , H01L23/31 , H01L23/64 , H01L25/04 , H01L25/16 , H01L25/18 , H05K1/02 , H05K1/18 , H05K3/30 , H05K3/32 , H05K3/34
CPC分类号： H01L23/642 , H01L21/4832 , H01L21/6835 , H01L23/13 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/16 , H01L2221/68377 , H01L2224/05554 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/83192 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H05K3/305 , H05K3/321 , H05K3/3442 , H05K3/3452 , H05K3/3463 , H05K2201/09036 , H05K2201/10636 , H05K2203/047 , Y02P70/611 , Y02P70/613 , H01L2924/00 , H01L2924/00014 , H01L2924/00015 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a hybrid integrated circuit wherein good connection without shorting etc. is possible when terminal electrodes of a chip component are attached on the pads formed in a conduction wiring layer by using solder. SOLUTION: In a wiring board, the chip component 37B wherein the terminal electrodes 39B, 39B are formed on both ends, the conduction wiring layer 35 wherein the pads 40, 40 are arranged which correspond to the terminal electrodes for attaching the chip component 37B by using solder, and overcoat resin 38 which coats the conduction wiring layer except the pads are formed. The hybrid integrated circuit has a constitution wherein a space 47 for flow stop which prevents shorting between the terminals by the flow of solder is arranged in an overcoat layer between the pads 40, 40 in the wiring board. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种混合集成电路，其中当通过使用焊料将芯片部件的端子电极附接到形成在导电布线层中的焊盘上时，可以实现良好的连接而不短路等。解决方案：在布线板中，在两端形成端子电极39B，39B的芯片部件37B，布置有与安装芯片的端子电极对应的焊盘40,40的导电布线层35 通过使用焊料形成部件37B，并且形成涂覆除了焊盘之外的导电布线层的外涂层树脂38。混合集成电路具有这样一种结构，其中通过焊料流动防止在端子之间短路的用于流动停止的空间47布置在布线板中的焊盘40,40之间的覆盖层中。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2011204862A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011204862A
公开(公告)日：2011-10-13
申请号：JP2010070098
申请日：2010-03-25
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： ITO MASAMI , NARUSE TOSHIMICHI , SAITO MASAYOSHI , TAKADA HIDEO
IPC分类号： H01L23/28 , H01L21/60 , H01L23/12
CPC分类号： H01L24/73 , H01L2224/37 , H01L2224/37147 , H01L2224/3754 , H01L2224/37599 , H01L2224/40 , H01L2224/40095 , H01L2224/40225 , H01L2224/73204 , H01L2224/8385 , H01L2224/8485 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To solve the problem with a conventional semiconductor device, wherein the device has poor heat dissipation properties and is not suited for mass productivity because of filling with an underfill material as well as difficulties in securing a gap between a semiconductor element and a conductive pattern.SOLUTION: In this semiconductor device, spacers 11A to 11D are arranged between a semiconductor element 2 and conductive patterns 9A to 9C, and a width W1 between the semiconductor element 2 and the conductive patterns 9A to 9C is a film thickness of the spacers 11A to 11D. By this structure, the width W1 of the gap in the lower surface of the semiconductor element 2 is maintained constantly, and the properties of filling the gap with a resin is improved. Moreover, transfer molding can be used to have a structure suited for mass productivity.
摘要翻译：要解决的问题：为了解决传统的半导体器件的问题，其中该器件具有差的散热性能，并且由于填充底部填充材料而不适合于批量生产，并且难以确保半导体元件和导电图案。解决方案：在该半导体器件中，间隔件11A至11D布置在半导体元件2和导电图案9A至9C之间，并且半导体元件2和导体图案9A至9C之间的宽度W1为间隔件11A至11D。通过这种结构，半导体元件2的下表面中的间隙的宽度W1保持恒定，并且提高了用树脂填充间隙的性质。此外，传递模塑可以用于具有适合于批量生产率的结构。

4. 发明专利

JP2006339233A Circuit device and method of manufacturing same 审中-公开
标题翻译：电路装置及其制造方法
公开(公告)号：JP2006339233A
公开(公告)日：2006-12-14
申请号：JP2005159166
申请日：2005-05-31
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NARUSE TOSHIMICHI , KOBAYASHI HAJIME , SUZUKI HARUO
IPC分类号： H01L23/12
CPC分类号： H01L24/97 , H01L2224/48091 , H01L2224/73265 , H01L2924/01322 , H01L2924/07802 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a circuit device with which connection structure of an external electrode and an electric conductive pattern is enforced. SOLUTION: A circuit device 10A of this configuration comprises an electric conduction pattern 11 consisting of a bonding pad 11A and a die pad 11B, a semiconductor device 12A adhered to the die pad 11B, and sealing resin 13 for sealing the circuit element and the electric conductive pattern 11 by exposing the rear surface of the electric conductive pattern 11. Moreover, a recess 11C in a shape concaved inside is formed in the rear surface of the electric conductive pattern 11 exposed from the sealing resin 13. An external electrode 15 is formed so that the recess 11C may be filled up. Therefore, the connection intensity of the external electrode 15 is improved. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种实现外部电极和导电图案的连接结构的电路装置。解决方案：该结构的电路装置10A包括由接合焊盘11A和芯片焊盘11B组成的导电图案11，附着在芯片焊盘11B上的半导体装置12A以及用于密封电路元件的密封树脂13 以及导电图案11的露出。此外，在从密封树脂13露出的导电图案11的后表面中形成凹陷形状的凹部11C。外部电极 15形成为可以填充凹部11C。因此，外部电极15的连接强度提高。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2014049604A Mounting board and circuit device using the same 审中-公开
标题翻译：安装板和使用该安装板的电路设备
公开(公告)号：JP2014049604A
公开(公告)日：2014-03-17
申请号：JP2012191274
申请日：2012-08-31
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KATO ATSUSHI , NARUSE TOSHIMICHI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To solve such a problem that the process is complicated to cause increase in cost when trying to obtain a thick conductive pattern for a large current and a thin conductive pattern for a small current on a substrate, and such a problem that a fine pattern cannot be drawn on the substrate when trying to use a thick conductive pattern for a large current also as a thin conductive pattern for a small current, because the film thickness is thick.SOLUTION: A mounting board has a core layer 52 composed of insulation resin, a first conductive pattern 53 provided on the surface side of the core layer 52, and a second conductive pattern 54 provided on the back side of the core layer 52. Interval d of the second conductive patterns 54 is set on the basis of the voltage being applied, and the second conductive pattern 54 is expanded to have a uniform interval on the basis of the set value. Consequently, the area of a conductive pattern on the back side is enlarged and heat dissipation effect is magnified.
摘要翻译：要解决的问题为了解决在试图获得大电流的粗导电图案和基板上的小电流的薄导电图案的过程复杂的过程复杂的问题，以及这样的问题，即由于薄膜厚度较厚，所以当试图对较大电流使用厚导电图形作为小电流的薄导电图案时，在基板上不能绘制精细图案。解决方案：安装板具有芯层52 绝缘树脂，设置在芯层52的表面侧的第一导电图案53和设置在芯层52的背面上的第二导电图案54.第二导电图案54的间隔d基于的电压，并且第二导电图案54根据设定值被扩展为具有均匀的间隔。因此，后侧的导电图案的面积被扩大，散热效果被放大。

6. 发明专利

JP2010237058A Sensor device, and method for manufacturing the same 审中-公开
标题翻译：传感器装置及其制造方法
公开(公告)号：JP2010237058A
公开(公告)日：2010-10-21
申请号：JP2009085850
申请日：2009-03-31
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOBAYASHI HAJIME , IGARASHI YUUSUKE , NARUSE TOSHIMICHI
IPC分类号： G01R33/02 , G01C17/28
摘要： PROBLEM TO BE SOLVED: To provide a sensor device to which a magnetometric sensor element is connected stably and electrically, and to provide a method for manufacturing the sensor device.
SOLUTION: The sensor device 10 includes a constitution mainly including a circuit board 12, sensor elements 14, 16, 18 arranged on the upper surface of the circuit board 12, and a sealing resin 32 for coating the sensor elements. The sensor element 14 and the sensor element 16 are provided with a sensor part 26 and a sensor part 28 respectively on each upper surface, and a connection pad provided on the upper surface is connected to a pad on the board via a metal thin wire 24. Meanwhile, in the sensor element 18, a connection pad 18A provided on the side face is connected to a thick post 35 arranged on the upper surface of the circuit board 12 via a solder 11.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种传感器装置，磁传感器元件稳定地和电连接到该传感器装置上，并提供一种用于制造传感器装置的方法。解决方案：传感器装置10包括主要包括电路板12，布置在电路板12的上表面上的传感器元件14,16,18和用于涂覆传感器元件的密封树脂32的结构。传感器元件14和传感器元件16分别在每个上表面上设置有传感器部分26和传感器部分28，并且设置在上表面上的连接焊盘通过金属细线24连接到板上的焊盘同时，在传感器元件18中，设置在侧面上的连接焊盘18A通过焊料11连接到布置在电路板12的上表面上的厚柱35上。（C）2011年， JPO＆INPIT

7. 发明专利

JP2008028135A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008028135A
公开(公告)日：2008-02-07
申请号：JP2006198783
申请日：2006-07-20
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NARUSE TOSHIMICHI , KOBAYASHI KENICHI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16 , H01L2924/01322 , H01L2924/01327 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, along with its manufacturing method, in which cracking is suppressed on a solder electrode which is used for flip chip mounting.
SOLUTION: The semiconductor device 10 mainly comprises a mounting substrate 12, a pad 13 (conductive pattern) formed on the surface of the mounting substrate 12, a semiconductor element 11 which is flip-chip mounted, a bonding electrode 16 formed on the lower surface of the semiconductor element 11, a post 15 formed on the surface of the bonding electrode 16, and a solder electrode 14 which is positioned between the lower surface of the post 15 and the upper surface of the pad 13 to connect them together. The surface of the pad 13 is not coated with a plating film, and the solder electrode 14 directly contacts the pad 13.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，其中在用于倒装芯片安装的焊料电极上抑制了开裂。解决方案：半导体器件10主要包括安装基板12，形成在安装基板12的表面上的焊盘13（导电图案），倒装芯片安装的半导体元件11，形成在半导体元件11的下表面，形成在接合电极16的表面上的柱15和位于柱15的下表面和垫13的上表面之间的焊料电极14，以将它们连接在一起。焊盘13的表面没有涂覆镀膜，焊料电极14直接接触焊盘13.版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2005277097A Resin sealed semiconductor device and method of manufacturing same 有权
标题翻译：树脂密封半导体器件及其制造方法
公开(公告)号：JP2005277097A
公开(公告)日：2005-10-06
申请号：JP2004088054
申请日：2004-03-24
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： IMAOKA SHUNICHI , YAMAGUCHI TAKESHI , USUI RYOSUKE , WATANABE HIROYUKI , NARUSE TOSHIMICHI , KATO ATSUSHI
IPC分类号： H01L23/28 , H01L21/44 , H01L21/56 , H01L23/31 , H01L25/065
CPC分类号： H01L21/565 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/01079 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To prevent connection failure caused by the disconnection of a bonding wire, the contact of the bonding wires, and the like caused by the flow of the wires at the time of sealing a resin sealed semiconductor device. SOLUTION: A semiconductor pellet 30 and a chip component 40 are provided on an insulating substrate 20, and are sealed with mold resin cast using a transfer mold method. The chip component 40 is arranged such that four sides of the semiconductor pellet 30 are surrounded thereby. The longitudinal direction of the chip component 40 surrounding the semiconductor pellet 30 faces a fixed direction. During resin injection, the insulating substrate 20 is set to a mold forming apparatus such that the longitudinal direction of the chip component 40 becomes substantially perpendicular to the direction of the flow of injected resin. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止由于在密封树脂密封的半导体器件时由导线的流动引起的接合线的断开，接合线等导致的连接故障。解决方案：半导体芯片30和芯片部件40设置在绝缘基板20上，并且使用转印模具法用模制树脂铸造密封。芯片部件40被布置成使得半导体芯片30的四个边被围绕。围绕半导体芯片30的芯片部件40的长度方向面向固定方向。在树脂注入期间，将绝缘基板20设定为成型装置，使得芯片部件40的纵向方向基本上垂直于注入树脂的流动方向。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2013058727A Mounting substrate and circuit device using the same 审中-公开
标题翻译：使用该安装基板和电路装置
公开(公告)号：JP2013058727A
公开(公告)日：2013-03-28
申请号：JP2012073468
申请日：2012-03-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KATO ATSUSHI , NARUSE TOSHIMICHI , IGARASHI YUUSUKE
IPC分类号： H01L23/12
CPC分类号： H05K1/0213 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H05K1/0265 , H05K1/141 , H05K3/427 , H05K2203/049 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To solve the problem in which: when an attempt is made to acquire a thick conductive pattern for high current and a thin conductive pattern for low current on a substrate, steps become complicated to cause a cost increase; but when an attempt is made to use the thick conductive pattern for high current as the thin conductive pattern for low current, a fine pattern cannot be drawn on the substrate only by thick film thickness.SOLUTION: A mounting substrate comprises: a core layer 52 composed of an insulating resin; a first conductive pattern 53 provided on a surface side of the core layer 52; a second thick conductive pattern 73 provided on a rear side of the core layer 52; and a Via 72 provided between a first electrode for high current in the first conductive pattern 53 and a second conductive pattern 301 provided so as to correspond to the first electrode. A resistance value of the Via 72 is lowered so that high current flows in the electrode on the rear side of the core layer via the Via 72. In addition, a signal can be taken out on the surface side because it can be relocated by a thick wiring 301 on the rear side.
摘要翻译：解决的问题为了解决这样一个问题，当在基板上获取大电流的粗导电图形和薄电极导电图案时，步骤变得复杂，导致成本增加; 但是当尝试使用厚电导图案作为高电流用作低电流的薄导电图案时，仅通过厚膜厚度不能在基板上绘制精细图案。解决方案：安装基板包括：由绝缘树脂构成的芯层52; 设置在芯层52的表面侧的第一导电图案53; 设置在芯层52的后侧的第二厚导电图案73; 以及设置在第一导电图案53中的用于高电流的第一电极和设置为对应于第一电极的第二导电图案301之间的通孔72。通孔72的电阻值降低，使得高电流通过通孔72在芯层的后侧的电极中流动。此外，可以在表面侧取出信号，因为它可以被重新定位背面的粗布301。版权所有（C）2013，JPO＆INPIT

10. 发明专利

JP2012080145A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012080145A
公开(公告)日：2012-04-19
申请号：JP2012015448
申请日：2012-01-27
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： NARUSE TOSHIMICHI , KOBAYASHI KENICHI , KOBAYASHI HAJIME
IPC分类号： H01L25/04 , H01L23/36 , H01L25/10 , H01L25/18
CPC分类号： H01L23/642 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/32225 , H01L2224/48 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19103 , H01L2924/30107 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device suitable for microfabrication and high integration of a semiconductor device in which a semiconductor chip and electronic components are mixedly mounted on a substrate and packaged.SOLUTION: An island, a spacer layer 3, and a discrete element 4 are stacked on a resin substrate 2 in this order. Chip capacitors 8 are formed between pad electrodes 6 and the spacer layer 3 on a first surface of the substrate 2. Pad electrodes 5 and the pad electrodes 6 are connected by bonding wires 10. On a second surface of the substrate 2, bump electrodes 11 are formed, which are electrically connected to the pad electrodes 6 via wiring. The position of the uppermost surface of the semiconductor chip 4 from the first surface of the substrate 2, that is the position of the pad electrodes 5, is raised by the spacer layer 3.
摘要翻译：要解决的问题：提供一种半导体器件，其适用于半导体器件的微细加工和高集成度，其中将半导体芯片和电子部件混合安装在基板上并被封装。解决方案：依次将岛，间隔层3和分立元件4堆叠在树脂基板2上。片状电容器8形成在衬底电极6和衬底2的第一表面上的间隔层3之间。焊盘电极5和焊盘电极6通过接合线10连接。在衬底2的第二表面上，凸起电极11 形成，其经由布线电连接到焊盘电极6。半导体芯片4的最上表面从衬底2的第一表面（即焊盘电极5的位置）的位置被间隔层3升高。（C）2012，JPO＆INPIT

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