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1. 发明专利

JP2010086990A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2010086990A
公开(公告)日：2010-04-15
申请号：JP2008250909
申请日：2008-09-29
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： KOUCHI SATOSHI , AMATATSU YOSHIMASA
IPC分类号： H01L21/76 , G03F7/20 , H01L21/027
摘要： PROBLEM TO BE SOLVED: To solve such a problem that a conventional manufacturing method of a semiconductor device cannot form an alignment mark for a light shielding film without a complicated manufacturing process. SOLUTION: The manufacturing method includes a step for forming a groove 9 and a separation trench 16 in a substrate 3 and an epitaxial layer 4, wherein a groove 15 for forming an alignment mark is formed in a scribe line region 2 and an HTO film 19 and a polycrystal silicon film 20 are deposited and processed in the groove 15 to form recesses 24 and 25 as an alignment mark. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了解决半导体器件的传统制造方法在没有复杂的制造工艺的情况下不能形成用于遮光膜的对准标记的问题。解决方案：制造方法包括在基板3和外延层4中形成槽9和分离槽16的步骤，其中在划线区域2中形成用于形成对准标记的槽15， HTO膜19和多晶硅膜20在槽15中沉积并处理，以形成作为对准标记的凹槽24和25。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010287750A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010287750A
公开(公告)日：2010-12-24
申请号：JP2009140685
申请日：2009-06-12
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： KOUCHI SATOSHI , ISHIZEKI HIROSHI , AKAISHI MINORU , SANO YOSHIAKI
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05555 , H01L2224/05569 , H01L2224/05572 , H01L2224/05624 , H01L2224/45 , H01L2224/45015 , H01L2224/45114 , H01L2224/45144 , H01L2224/45147 , H01L2224/48 , H01L2224/48091 , H01L2224/48463 , H01L2224/48624 , H01L2224/48799 , H01L2924/00011 , H01L2924/00015 , H01L2924/01004 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/05042 , H01L2924/10253 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/00014 , H01L2924/01203 , H01L2924/01204 , H01L2224/05556 , H01L2224/48824 , H01L2924/00 , H01L2924/01006 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that has a Cu wire mounted on a Cu wiring layer.
SOLUTION: The semiconductor device includes a protection layer 6 formed on a silicon substrate 1, the Cu wiring layer 9 formed on the protection layer 6 and electrically connecting with a semiconductor element formed on the silicon substrate 1, a resin film 10 formed on the protection layer 6 to cover the Cu wiring layer 9, a pad electrode 12 connecting with the Cu wiring layer 9 through an opening region 11 formed in the resin film 10, and the Cu wire 13 wire-bonded onto the pad electrode 12.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有安装在Cu布线层上的Cu线的半导体器件。解决方案：半导体器件包括形成在硅衬底1上的保护层6，形成在保护层6上并与形成在硅衬底1上的半导体元件电连接的Cu布线层9，形成的树脂膜10 在保护层6上覆盖Cu布线层9，通过形成在树脂膜10中的开口区域11与Cu布线层9连接的焊盘电极12和引线键合到焊盘电极12上的Cu线13。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2009088002A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009088002A
公开(公告)日：2009-04-23
申请号：JP2007252206
申请日：2007-09-27
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： AMATATSU YOSHIMASA , KOUCHI SATOSHI , OKABE KATSUYA
IPC分类号： H01L21/3205 , H01L23/12 , H01L23/52
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To overcome the problem of a conventional semiconductor device that an electrode for connection is oxidized by gas generated from an SOG film of an interlayer insulating layer during degassing, and thereby it is hard to reduce the resistance on the electrode for connection. SOLUTION: In the semiconductor device, an opening region 29 is formed in a TEOS film 27 and an SiN film 28 on an electrode 26 for connection. In the opening region 29, a metal layer 34 for plating and a Cu plating layer 36 are laminated on the electrode 26 for connection. When the electrode 26 for connection is exposed from the opening region 29, SOG films 14 and 22 are not exposed and since the electrode 26 for connection is not oxidized by gas generated from the SOG films 14 and 22 during degassing, resistance on the electrode 26 for connection is reduced. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题为了克服在脱气期间由层间绝缘层的SOG膜产生的气体氧化连接用电极的现有的半导体装置的问题，因此难以降低电阻用于连接的电极。解决方案：在半导体器件中，在TEOS膜27和用于连接的电极26上的SiN膜28上形成开口区域29。在开口区域29中，用于电镀的金属层34和Cu镀层36层叠在电极26上用于连接。当用于连接的电极26从开口区域29暴露时，SOG膜14和22不暴露，并且由于用于连接的电极26在脱气期间不被SOG膜14和22产生的气体氧化，所以电极26上的电阻为连接减少。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2006049689A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006049689A
公开(公告)日：2006-02-16
申请号：JP2004230643
申请日：2004-08-06
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： OKUDA TOSHIHIRO , KOUCHI SATOSHI , SANO TORU
IPC分类号： H01L21/76 , H01L21/331 , H01L29/732
摘要： PROBLEM TO BE SOLVED: To solve the problem that junction leakage current occurs between the collector and the base in the conventional semiconductor device.
SOLUTION: In the semiconductor device, the side wall 41 of a trench 11 is formed in the step structure. A silicon oxide film 32 and a TEOS film 33 are formed between the upper end 40 of the trench 11 and a base extraction electrode 9 to prevent them from abutting against each other. Due to this structure, the concentration of thermal stress on the upper end 40 of the trench 11 can be eased, resulting in suppressing the occurrence of crystal defects from the upper end 40 of the trench 11. Even if crystal defects occur, the crystal defects are kept away from the passage of the base current and thereby the junction leakage current can be reduced between the collector and the base.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了解决传统的半导体器件中集电极和基极之间发生结漏电流的问题。解决方案：在半导体器件中，沟槽11的侧壁41形成在台阶结构中。在沟槽11的上端40和基极引出电极9之间形成氧化硅膜32和TEOS膜33，以防止它们相互抵接。由于这种结构，能够缓和沟槽11的上端40的热应力集中，从而抑制从沟槽11的上端40发生晶体缺陷。即使发生晶体缺陷，晶体缺陷远离基极电流的通过，从而可以在集电极和基极之间减小结漏电流。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2006049687A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006049687A
公开(公告)日：2006-02-16
申请号：JP2004230641
申请日：2004-08-06
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOUCHI SATOSHI , OKUDA TOSHIHIRO , IHARA YOSHIKAZU
IPC分类号： H01L21/768 , H01L21/331 , H01L29/732
摘要： PROBLEM TO BE SOLVED: To solve a conventional problem of laborious manufacturing process and increased manufacturing cost, because an insulating film is formed as an etching resistance film on the surface of a semiconductor layer when forming a contact hole in the insulating layer deposited on the surface of semiconductor layer.
SOLUTION: A process for etching a silicon oxide film 8 and TEOS films 9 and 20 on the surface of a diffusion region 4 of a collector region is separated from a process for etching TEOS films 12 and 20 on the surface of a base taking-out electrode 16. A cobalt silicide film 21 is formed on the surface of diffusion region 4 and that of base taking-out electrode 16 which are exposed. The cobalt silicide film 21 is used as an etching resistance film when forming contact holes 25, 26, and 27, to prevent overetching.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题为了解决繁琐的制造工艺和增加的制造成本的常规问题，由于在形成绝缘层中的接触孔时在半导体层的表面上形成绝缘膜作为耐蚀刻性膜在半导体层的表面。解决方案：在集电区域的扩散区域4的表面上蚀刻氧化硅膜8和TEOS膜9和20的工艺与在基底表面上蚀刻TEOS膜12和20的工艺分离取出电极16.在扩散区域4的表面和露出的基极取出电极16的表面上形成硅化钴膜21。当形成接触孔25,26和27时，硅化钴膜21用作耐腐蚀性膜，以防止过蚀刻。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006049685A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006049685A
公开(公告)日：2006-02-16
申请号：JP2004230638
申请日：2004-08-06
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOUCHI SATOSHI , OKUDA TOSHIHIRO
IPC分类号： H01L21/76 , H01L21/331 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/763
摘要： PROBLEM TO BE SOLVED: To solve a conventional problem of occurrence of a junction leak current between a collector and a base due to crystal defect of a slot end adjoining a base region.
SOLUTION: An opening 17 is so formed on a silicon oxide film 15 and a TEOS film 16 as to allow separation distance t1 from an upper end part 18 of a slot part 8. The opening 17 is utilized to form a base taking-out electrode 21. An external base region 19 is formed from the base taking-out electrode 21 by solid-phase diffusion. Here, a separation distance t2 is allowed between the external base region 19 and the upper end 18 of the slot part 8. By this manufacturing method, occurrence of junction leak current between a collector and a base is suppressed.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了解决由于与基底区域相邻的槽端部的晶体缺陷导致集电体与基体之间的结漏电流的常见问题。解决方案：开口17形成在氧化硅膜15和TEOS膜16上，以允许与槽部分8的上端部分18的间隔距离t1。开口17用于形成基部外部基极区域19由基极取出电极21通过固相扩散形成。这里，在外部基部区域19和槽部8的上端部18之间允许间隔距离t2。通过该制造方法，抑制集电体与基底之间的结漏电流的发生。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2006013341A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006013341A
公开(公告)日：2006-01-12
申请号：JP2004191573
申请日：2004-06-29
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： KOUCHI SATOSHI , HATA HIROTSUGU
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/763 , H01L21/76224
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of semiconductor device which can prevent the break of wire even when a wiring layer is formed on the upper surface of a recess in an isolating region and can form a passive element such as a capacitance element or the like because a flat surface can be substantially formed in the isolating region.
SOLUTION: In the manufacturing method of semiconductor device, a part of the HTO film 13 covering the internal wall of a trench 12 is removed when a silicon oxide film 4 to be used for STI method is removed thereby forming a recess 16 in the isolating region. Thereafter, a TEOS film 17 is deposited on the upper surface of an epitaxial layer 3 including the recess 16, and an insulating spacer 18 is embedded into the recess 16 through the etching back.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了提供即使当在隔离区域的凹部的上表面上形成布线层时也可以防止线断裂的半导体器件的制造方法，并且可以形成无源元件，例如电容元件等，因为平坦表面可以基本形成在隔离区域中。解决方案：在半导体器件的制造方法中，当去除用于STI法的氧化硅膜4时，去除覆盖沟槽12的内壁的HTO膜13的一部分，从而形成凹槽16 隔离区域。此后，在包括凹部16的外延层3的上表面上沉积TEOS膜17，并且通过蚀刻将绝缘间隔物18嵌入到凹部16中。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2010171386A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010171386A
公开(公告)日：2010-08-05
申请号：JP2009259714
申请日：2009-11-13
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： KOUCHI SATOSHI , AKAISHI MINORU , ISHIZEKI HIROSHI , SANO YOSHIAKI
IPC分类号： H01L21/60 , H01L21/3205 , H01L23/52
CPC分类号： H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05083 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05556 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48844 , H01L2224/48855 , H01L2224/48864 , H01L2224/85 , H01L2224/85205 , H01L2924/00011 , H01L2924/00015 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/05042 , H01L2924/10253 , H01L2924/13091 , H01L2924/00014 , H01L2924/00 , H01L2924/01006
摘要： PROBLEM TO BE SOLVED: To prevent failure, such as, wiring separations or cracks in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion located above the copper wiring. SOLUTION: The semiconductor device includes a copper wiring 8 formed above a semiconductor substrate 1; a plated layer 10 formed so as to cover a top surface and side surfaces of the copper wiring 8; and a copper wire 11, which is wire-bonded above the copper wiring 8 with the plated layer 10 therebetween. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了防止在铜线上的部分上的铜线引线接合形成的半导体器件中的诸如铜线之间的绝缘膜中的布线分离或裂纹的故障。解决方案：半导体器件包括形成在半导体衬底1上的铜布线8; 形成为覆盖铜布线8的上表面和侧面的镀层10; 以及铜线11，其在铜布线8的上方被引线接合，并且其间具有镀层10。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2008270366A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008270366A
公开(公告)日：2008-11-06
申请号：JP2007108548
申请日：2007-04-17
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： AMATATSU YOSHIMASA , AKAISHI MINORU , KOUCHI SATOSHI , OKABE KATSUYA , SANO YOSHIAKI , YAMANE AKIRA
IPC分类号： H01L21/768 , H01L21/3205 , H01L23/12 , H01L23/52
CPC分类号： H01L21/76816 , H01L21/32051 , H01L21/76838 , H01L21/76843 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53223 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/0401 , H01L2224/05008 , H01L2224/05096 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05548 , H01L2224/05554 , H01L2224/05567 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/11462 , H01L2224/1148 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/3025 , H01L2924/00014 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To solve the problem wherein connection resistance values among wiring layers are difficult to reduce owing to oxide films formed among wiring layers in a conventional semiconductor device. SOLUTION: In the semiconductor device, an opening section 22 is formed to a spin coating resin film 21 on first metallic layers 14 to 18 embedding opening regions 8 to 12 connecting a first wiring layer 3 and a second wiring layer. A Cr layer configuring a metallic layer 23 for a plating and a Cu plating layer 24 are connected in the opening section 22. According to this configuration, sections among crystal grains are widened in the Cr layer on the first metallic layers 14 to 18, and a coarse region is formed. The alloy layer of a second metallic layer 19 and the Cu plating layer 24 is formed in the coarse region of the Cr layer, and the connection resistance value is reduced. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题为了解决由于传统的半导体器件中的布线层之间形成的氧化膜难以降低布线层之间的连接电阻值的问题。解决方案：在半导体器件中，在第一金属层14至18上的旋涂树脂膜21上形成开口部22，该第一金属层14至18嵌入连接第一布线层3和第二布线层的开口区域8至12。在开口部22中连接构成电镀用金属层23和Cu镀层24的Cr层。根据该结构，在第一金属层14〜18的Cr层中，晶粒中的部分变宽，形成粗糙区域。在Cr层的粗糙区域形成第二金属层19和Cu镀层24的合金层，连接电阻值降低。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2008244134A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008244134A
公开(公告)日：2008-10-09
申请号：JP2007082434
申请日：2007-03-27
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： AMATATSU YOSHIMASA , AKAISHI MINORU , KOUCHI SATOSHI , OKABE KATSUYA , SANO YOSHIAKI , YAMANE AKIRA
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L23/293 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/03462 , H01L2224/0347 , H01L2224/0401 , H01L2224/05014 , H01L2224/05022 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05567 , H01L2224/05572 , H01L2224/05647 , H01L2224/13007 , H01L2224/13022 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/3025 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To solve the problem that the resistance on a pad electrode is less apt to be reduced by an oxide film on the surface of the pad electrode in the conventional semiconductor device. SOLUTION: A metal layer 4 for an oxidation-resistant film is formed on a pad electrode 3 in a semiconductor device. The metal layer 4 for the oxidation-resistant film is exposed from an opening region 8 in a spin-coat resin film 7 on the pad electrode 3, and a metal layer 9 for plating and a copper-plating layer 10 are formed on the metal layer 4 for the oxidation-resistant film. According to this structure, on the pad electrode 3, the upper surface of the pad electrode 3 is less apt to be oxidized, and the metal layer 4 for the oxidation-resistant film with an extremely smaller resistant value than an oxidized film is made to serve as a current channel and the resistance on the pad electrode 3 is reduced. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题为了解决现有的半导体装置中的焊盘电极的表面上的氧化膜难以降低焊盘电极的电阻的问题。解决方案：在半导体器件中的焊盘电极3上形成用于抗氧化膜的金属层4。用于抗氧化膜的金属层4从焊盘电极3上的旋涂树脂膜7中的开口区域8露出，并且在金属上形成用于电镀的金属层9和镀铜层10 层4用于抗氧化膜。根据该结构，在焊盘电极3上，焊盘电极3的上表面不易氧化，并且将耐氧化膜的耐氧化膜的金属层4比氧化膜制成为作为电流通道，并且焊盘电极3上的电阻降低。版权所有（C）2009，JPO＆INPIT

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