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1. 发明专利

JP2009038388A Semiconductor device having bit line landing pad and borderless contact on bit line stud with localized etch stop material layer and fabricating method thereof 审中-公开
标题翻译：具有本地化消弧材料层及其制造方法的位线线路板上的位线接线和无边界接触的半导体器件
公开(公告)号：JP2009038388A
公开(公告)日：2009-02-19
申请号：JP2008238574
申请日：2008-09-17
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： YANA GENSEKI , KO YUSHO , JEONG HONG-SIK , KIM KINAN
IPC分类号： H01L21/302 , H01L21/768 , G11C7/00 , H01L21/3065 , H01L21/4763 , H01L21/60 , H01L21/8242 , H01L23/522 , H01L27/10 , H01L27/108
CPC分类号： H01L21/76897 , H01L21/76829 , H01L21/76834 , H01L27/10882 , H01L27/10894
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has a bit line landing pad and a borderless contact with a localized etch-stop material layer and has a relatively dense structure, and a fabricating method thereof.
SOLUTION: Inter-layer constact studs 220a and 220b are formed, and a conductive line 222 is provided over the inter-layer contact stud 220b. A first etch-stop material layer 224a and a second etch-stop material layer 224b are selectively provided over them. The conductive line 222 is provided with a side wall insulating film 226. Material of the first etch-stop material layer and that of the side wall insulating film are different by etch selectivity. These etch-stop material layers allow outgassing of impurities during subsequent processes and serve as an alignment target when forming an upper contact hole 229a.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其具有位线着色焊盘和与局部蚀刻停止材料层无边界接触并且具有相对致密的结构及其制造方法。
解决方案：形成层间结构螺柱220a和220b，并且在层间接触螺柱220b之上设置导线222。在其上选择性地提供第一蚀刻停止材料层224a和第二蚀刻停止材料层224b。导电线222设置有侧壁绝缘膜226.第一蚀刻停止材料层和侧壁绝缘膜的材料通过蚀刻选择性而不同。这些蚀刻停止材料层在后续工艺中允许杂质脱气，并且当形成上接触孔229a时用作对准靶。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2002184861A SEMICONDUCTOR ELEMENT HAVING NON-BOUNDARY CONTACT AND BIT LINE LANDING PAD ON BIT LINE STUD HAVING LOCAL ETCHING STOP SUBSTANCE LAYER, AND ITS FABRICATING METHOD 审中-公开
公开(公告)号：JP2002184861A
公开(公告)日：2002-06-28
申请号：JP2001307825
申请日：2001-10-03
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YANA GENSEKI , KO YUSHO , JEONG HONG-SIK , KIM KINAN
IPC分类号： H01L21/302 , G11C7/00 , H01L21/3065 , H01L21/4763 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide such an etching stop substance layer as patterning is effected only on a part of a lower interlayer insulation film so that degassing is allowed during fabrication process. SOLUTION: A semiconductor element has first and second circuit regions arranged side by side in a first insulation film. The first circuit region includes a conductive line and the second circuit region includes a stud. First and second etching stop substance layers are formed, respectively, on the first and second circuit regions wherein the first etching stop substance layer forms at least one spacer on the sidewall of the conductive line and the second etching stop substance layer is patterned selectively in the second circuit region to cover a region including the stud. A multilayer circuit, e.g. a memory element, having a relatively compact structure can be fabricated by this system.

3. 发明专利

JP2002313956A SEMICONDUCTOR MEMORY ELEMENT AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002313956A
公开(公告)日：2002-10-25
申请号：JP2002057944
申请日：2002-03-04
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YANA GENSEKI , SONG SANG-HO , KIM KI-NAM , JEONG HONG-SIK
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory element and its manufacturing method. SOLUTION: A part which connects a lower conductive layer formed on a semiconductor substrate across a first inter-layer insulating layer and an upper conductive layer formed above the lower conductive layer across a second inter-layer insulating layer is divided into one or more plugs and pads. The one or more plugs are formed at lower end parts in the first and second inter- layer insulating layers and the second inter-layer insulating layer is divided into a number of subordinate inter-layer insulating layers so that differences in size between the upper widths and lower widths of the respective pads do not become large. Then the pad formed at the upper end part of the second inter-layer insulating layer is so wide that the upper conductive layer that the pad comes into contact with does not come into contact with another adjacent upper conductive layer.

4. 发明专利

JP2002033402A SEMICONDUCTOR, MEMORY ELEMENT HAVING FLOATING BODY EFFECT REMOVED AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002033402A
公开(公告)日：2002-01-31
申请号：JP2001177544
申请日：2001-06-12
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM CHANG-HYUN , KIM KYUNG-HO , YANA GENSEKI
IPC分类号： C12S5/00 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory element which is increased in immunity to external noise and has floating body effect removed. SOLUTION: A memory element is equipped with a semiconductor substrate, bit lines which are embedded adjacently to the top surface of the semiconductor substrate and arrayed in parallel, word lines which are formed on the semiconductor substrate while insulated from and crossing the bit lines, and vertical access transistors which are formed in unit memory cell areas where the bit lines and word lines cross each other and have 1st source/drain areas, channel areas, and 2nd source/drain areas vertically on the bit lines across a gate insulating film along part, of the side wall of the word lines; and body areas including the channel areas of the access transistors are mutually connected together into one body.

5. 发明专利

JP2002246466A SEMICONDUCTOR DEVICE HAVING MULTILAYER WIRING STRUCTURE, AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2002246466A
公开(公告)日：2002-08-30
申请号：JP2001386750
申请日：2001-12-19
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YANA GENSEKI , KIM KI-NAM , JEONG HONG-SIK
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a multilayer wiring structure and to provide a method for manufacturing it. SOLUTION: A semiconductor substrate 200 is formed and an interlayer insulating film 204 is formed on the semiconductor substrate 200. A first contact stud 208 the width of, whose entrance adjacent to the surface of the interlayer insulating film 204 is still larger than its contact part near the substrate 200, is formed inside the interlayer insulating film 204. A second contact stud 208b, which is spaced from the first contact stud 208 by a specified distance, is formed inside the interlayer insulating film 204. A landing pad 210, which has a width larger than that of the second contact stud 208b, is provided on the interlayer insulating film 204, in such a way that it is in contact with the surface of the second contact stud 208b. The width of the contact part and that of the entrance part of the second contact stud 208b are almost equal. At least one spacer 214 made of an etching blocking layer can be formed on both sidewalls of the landing pad 210 and an etching blocking layer 212 can be provided on the top of the landing pad 210.

6. 发明专利

JP2003068742A Semiconductor element and its manufacturing method 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：JP2003068742A
公开(公告)日：2003-03-07
申请号：JP2002179081
申请日：2002-06-19
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： YANA GENSEKI , KIM KI-NAM
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/485
CPC分类号： H01L24/02 , H01L2924/01004 , H01L2924/01033 , H01L2924/14 , H01L2924/30105
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element which can prevent misalignment in forming a contact hole to expose a fine pattern.
SOLUTION: The semiconductor element consists of a semiconductor substrate 60 including a conductive region and insulating region, a conductive pattern formed on the conductive region of the semiconductor substrate 60, an auxiliary pattern composed of a conductive layer positioned adjacent to the conductive pattern, and an inter-layer dielectric film 66 which is formed on the semiconductor substrate 60 and has a contact hole 68 exposing the conductive pattern and auxiliary pattern at the same time. Thereby, the auxiliary pattern which does not electrically affect an area adjacent to the fine pattern is formed in order to prevent the misalignment when forming a contact hole or via hole to make the fine pattern open.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种半导体元件，其可以防止形成接触孔中的未对准以露出精细图案。解决方案：半导体元件由包括导电区域和绝缘区域的半导体衬底60，形成在半导体衬底60的导电区域上的导电图案，由与导电图案相邻定位的导电层构成的辅助图案，以及层间电介质膜66，其形成在半导体基板60上，并且具有同时暴露导电图案和辅助图案的接触孔68。由此，为了防止在形成接触孔或通路孔时形成未对准的微细图形打开，形成不影响与微细图案相邻的区域的辅助图案。

7. 发明专利

JP2003023108A Integrated circuit device provided with self-alignment contact pad having increased alignment margin and manufacturing method therefor 审中-公开
标题翻译：具有自对准接触垫的集成电路装置，具有增加的对准边界及其制造方法
公开(公告)号：JP2003023108A
公开(公告)日：2003-01-24
申请号：JP2002156498
申请日：2002-05-29
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： YANA GENSEKI , KIM KI-NAM
IPC分类号： H01L21/768 , H01L21/60 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108
CPC分类号： H01L21/76897
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit device having a self-alignment contact pad and to provide the manufacturing method.
SOLUTION: An element separating film for limiting multiple active areas separated at equal intervals in vertical/lateral directions are formed on a semiconductor substrate. Multiple word line structures extending on the substrate are formed on the substrate so that one active area crosses two active areas. A source area is formed in the active area outside the structure, and a drain area is formed in the active area between the structures. The self-alignment contact pads are formed in a row where the active area is formed in the areas between the structures. The self-alignment contact pad includes a first-self- alignment contact pad which is brought into contact with the source area, a second self-alignment contact pad which is brought into contact with the drain area, and a third self-alignment contact pad formed on the element separation film.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种具有自对准接触焊盘的集成电路器件，并提供制造方法。解决方案：在半导体衬底上形成用于限制在垂直/横向相等间隔分开的多个有源区的元件分离膜。在基板上形成延伸在基板上的多个字线结构，使得一个有效区域跨过两个有效区域。源区域形成在结构外部的有源区域中，并且在结构之间的有源区域中形成漏极区域。自对准接触焊盘形成为在结构之间的区域中形成有源区的行。自对准接触焊盘包括与源极区域接触的第一自对准接触焊盘，与漏极区域接触的第二自对准接触焊盘和第三自对准接触焊盘形成在元件分离膜上。

8. 发明专利

JP2002184868A SEMICONDUCTOR ELEMENT TOGETHER WITH ITS MANUFACTURING METHOD COMPRISING BIT LINE LANDING PAD AND BORDERLESS CONTACT ON BIT LINE STUD COMPRISING LOCAL ETCHING PREVENTING LAYER FORMED IN VOID REGION 审中-公开
公开(公告)号：JP2002184868A
公开(公告)日：2002-06-28
申请号：JP2001328341
申请日：2001-10-25
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YANA GENSEKI , SONG SANG-HO , JEONG HONG-SIK , KIM KINAN
IPC分类号： H01L21/768 , H01L21/8242 , H01L23/02 , H01L23/48 , H01L23/52 , H01L27/10 , H01L27/108 , H01L29/40
摘要： PROBLEM TO BE SOLVED: To provide an etching preventing layer where only a part of a lower inter-layer insulating layer is selectively patterned for allowing outgassing in a manufacturing process thereafter. SOLUTION: An etching preventing layer is provided in a multilayer circuit layer by a selective method so that an impurity is outgassed during the manufacturing process. The etching preventing layer is so formed above the lower stud as to act as an alignment target while forming an upper stud formed in an upper layer. Thus, there are provided a first insulating layer 202 formed above a substrate, a second insulating layer 302 formed on the first insulating layer, a stud 220a so formed as to penetrate the first and second insulating layers, a third insulating layer 204 formed at the top of the stud, and a first pad comprising etching preventing layers formed above the upper surface of the stud and below the third insulating layer.

9. 发明专利

JP2002151588A SEMICONDUCTOR DEVICE HAVING BIT-LINE LANDING PAD AND NO BOUNDARY CONTACT ON BIT-LINE STUD PROVIDED WITH ETCHING STOP LAYER, AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2002151588A
公开(公告)日：2002-05-24
申请号：JP2001260224
申请日：2001-08-29
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： JEONG HONG-SIK , YANA GENSEKI , KIM KI-NAM
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a circuit and method wherein the precision of its etching depth is secured by forming its etching stop layer having a different etching selectivity from its underlay insulation film, and its etching stop layer so exists only in the peripheral region of its elements as to make possible the degassings of its constituent elements which occur during the processes following to constituting the elements, and as to make possible the following alloy processes for repairing properly the defects of its underlay contacts and its transistors. SOLUTION: In the manufacturing method of the semiconductor device, an etching stop layer is provided selectively between the layers of a multilayer circuit in consideration of degassing impurities during its continuous manufacturing processes. The etching stop layer is so formed on an underlay stud as to serve as an alignment target during forming an upper layer stud to be formed in the upper layer which is coupled to the underlay stud. By such a method, the multilayer circuits, e.g. memory elements can be manufactured in a comparably dense layout.

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