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1. 发明专利

JP2008210503A Nonvolatile memory device and its driving method 有权
标题翻译：非易失性存储器件及其驱动方法
公开(公告)号：JP2008210503A
公开(公告)日：2008-09-11
申请号：JP2008046477
申请日：2008-02-27
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK KI TAE , KIM KI-NAM , LEE YEONG-TAEK
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/30 , G11C16/3454
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile memory device and especially a driving method of a nonvolatile memory device. SOLUTION: The driving method of a nonvolatile memory device includes: a step in which a structural position of a memory cell to be driven is determined; and a step in which driving is made under driving conditions, which correspond to the distribution of threshold voltages which belong to the memory cell, according to the result of the determination. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供非易失性存储装置，特别是非易失性存储装置的驱动方法。解决方案：非易失性存储器件的驱动方法包括：确定要驱动的存储单元的结构位置的步骤; 以及根据确定的结果，在与驱动条件对应于属于存储单元的阈值电压的分布的驱动条件下进行驱动的步骤。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008103729A Semiconductor device and method for forming it 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：JP2008103729A
公开(公告)日：2008-05-01
申请号：JP2007271758
申请日：2007-10-18
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KWAK DONG-HWA , PARK JAE-KWAN , SIM JAE-HWANG , KIM JIN-HO , KIM KI-NAM
IPC分类号： H01L21/768 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/76897 , H01L21/76816 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To provide a method for forming wiring which is electrically connected to a lower region through a contact. SOLUTION: The method for forming the wiring includes steps of: forming an insulating film on a substrate which has a plurality of first regions and a plurality of second regions which are arranged between the first regions; forming a plurality of first wiring on the insulating film which are connected electrically to the corresponding first regions through first contacts penetrating the insulating film; forming spacers on side faces of the first wiring; removing the insulating film positioned between the adjacent spacers so as to form a plurality of contact holes in which the corresponding second regions are exposed between the adjacent first contacts; and forming a plurality of second contacts which are filled in the corresponding contact holes to form a plurality of second wiring which are connected electrically to the corresponding second contacts. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过接触电连接到下部区域的布线的形成方法。解决方案：用于形成布线的方法包括以下步骤：在具有多个第一区域和布置在第一区域之间的多个第二区域的基板上形成绝缘膜; 在所述绝缘膜上形成多个第一布线，所述多个第一布线通过穿过所述绝缘膜的第一触点与相应的第一区域电连接; 在所述第一布线的侧面上形成间隔物; 去除位于相邻间隔物之间的绝缘膜，以便形成多个接触孔，相邻的第二区域在相邻的第一接触件之间露出; 以及形成多个第二触点，其填充在相应的接触孔中以形成多个第二布线，所述多个第二布线电连接到相应的第二触点。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006054046A Method of operating magnetic ram device using spin injection, and magnetic ram device 有权
标题翻译：使用旋转注射操作磁性RAM器件的方法和磁性RAM器件
公开(公告)号：JP2006054046A
公开(公告)日：2006-02-23
申请号：JP2005234722
申请日：2005-08-12
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JEONG WON-CHEOL , KIM KI-NAM , JEONG HONG-SIK , JEONG GI-TAE , PARK JAE-HYUN
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08
CPC分类号： G11C11/16
摘要： PROBLEM TO BE SOLVED: To provide a method for operating a magnetic RAM device including a memory cell having a magnetic tunnel junction structure on a substrate. SOLUTION: The method is provided for operating the magnetic RAM device including the memory cell having the magnetic tunnel junction structures 41a, 41b on the substrate 1. The method includes steps of: impressing a writing current pulse through the magnetic tunnel junction structures 41a, 41b; and impressing a writing magnetic field pulse onto the magnetic tunnel junction structures, wherein at least a portion of the writing magnetic field pulse is overlapping in time with respect to at least a portion of the writing current pulse. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种在基板上操作包括具有磁性隧道结结构的存储单元的磁性RAM器件的方法。解决方案：提供了用于操作包括在衬底1上具有磁性隧道结结构41a，41b的存储单元的磁性RAM器件的方法。该方法包括以下步骤：通过磁性隧道结结构施加写入电流脉冲 41a，41b; 并将写入磁场脉冲施加到磁性隧道结结构上，其中写入磁场脉冲的至少一部分相对于写入电流脉冲的至少一部分在时间上重叠。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2008159244A Method of programming in nonvolatile memory device, and nonvolatile memory device applying this program 有权
标题翻译：在非易失性存储器件中编程的方法和应用本程序的非易失性存储器件
公开(公告)号：JP2008159244A
公开(公告)日：2008-07-10
申请号：JP2007326144
申请日：2007-12-18
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK KI TAE , LEE YEONG-TAEK , KIM KI-NAM , KIM DOO-GON
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04
CPC分类号： G11C16/3418 , G11C16/24 , G11C16/3427
摘要： PROBLEM TO BE SOLVED: To provide a method of programming in a nonvolatile memory device, and a nonvolatile memory device in which reduction of program disturbance of a memory cell can be expected without increasing a programming time. SOLUTION: When programming is performed in the nonvolatile memory device in which at least one or more pulses are applied successively to a selection word line, pre-charge voltage is applied to an even bit line and an odd bit line so that pre-charge voltage and boost voltage being higher than this pre-charge voltage are charged alternately. Bit line voltage to which the bit value of entered data corresponds is applied to a selection bit line out of these even bit line and odd bit line. By this method, program disturbance can be reduced while preventing delay of a programming time. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在非易失性存储器件中编程的方法，以及非易失性存储器件，其中可以预期在不增加编程时间的情况下减小存储器单元的编程干扰。解决方案：当在至少一个或多个脉冲连续施加到选择字线的非易失性存储器件中执行编程时，预充电电压被施加到偶数位线和奇数位线，使得预充电高于该预充电电压的充电电压和升压电压交替地充电。输入数据的位值对应的位线电压被施加到这些偶数位线和奇数位线中的选择位线。通过这种方法，可以减少程序干扰，同时防止编程时间的延迟。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007294995A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007294995A
公开(公告)日：2007-11-08
申请号：JP2007174271
申请日：2007-07-02
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIM KI-NAM , JUNG DONG-JIN
IPC分类号： H01L21/8246 , H01L21/8247 , H01L21/02 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor which prevents the deterioration on the uses at high temperatures and of repeated read/wright, and has a large sensing margin.
SOLUTION: The semiconductor device includes a conductive layer formed on an active region of a semiconductor substrate having an element separation region to define the active region and a non-active region; a first insulating film formed on the semiconductor substrate with the conductive layer included; a capacitor including a lower electrode, a ferroelectric film and an upper electrode, which are laminated sequentially on the first insulating film, and formed such that the upper electrode and the ferroelectric film are overlapped on a part of the lower electrode; a second insulating film formed on the first insulating film with the capacitor included; a first opening formed so as to penetrate the second insulating film and exposing the lower electrode; a second opening which penetrates the second insulating film and the first insulating film and exposes an upper surface of the semiconductor substrate of a side of the conductive layer; and a contact layer to electrically connect the lower electrode and the semiconductor substrate of the side of the conductive layer through the first opening and the second opening.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体，其防止高温下的使用劣化和重复的读/写，并且具有大的感测余量。解决方案：半导体器件包括形成在具有元件分离区域的半导体衬底的有源区上以限定有源区和非有源区的导电层; 形成在具有导电层的半导体衬底上的第一绝缘膜; 包括下电极，铁电体膜和上电极的电容器，其顺序层叠在第一绝缘膜上，并且形成为使得上电极和铁电体膜重叠在下电极的一部分上; 形成在具有电容器的第一绝缘膜上的第二绝缘膜; 形成为穿透所述第二绝缘膜并使所述下电极露出的第一开口; 第二开口，其穿过所述第二绝缘膜和所述第一绝缘膜，并且暴露所述半导体衬底的所述导电层侧的上表面; 以及接触层，以通过第一开口和第二开口电连接导电层侧面的下电极和半导体衬底。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2013098553A Graphene transistor having air gap, hybrid transistor including the same, and manufacturing method for the same 有权
标题翻译：具有气隙的石墨晶体管，包括其的混合晶体管及其制造方法
公开(公告)号：JP2013098553A
公开(公告)日：2013-05-20
申请号：JP2012233438
申请日：2012-10-23
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： CHUNG HYUN-JONG , JOUNG WOO-IN , KIM KI-NAM
IPC分类号： H01L29/786 , H01L21/28 , H01L21/283 , H01L21/336 , H01L51/05 , H01L51/30 , H01L51/40
CPC分类号： H01L29/772 , B82Y40/00 , H01L21/8232 , H01L27/0688 , H01L29/1606 , H01L29/41758 , H01L29/518 , H01L29/778 , H01L29/78606 , H01L29/78684 , Y10S977/734 , Y10S977/842 , Y10S977/938
摘要： PROBLEM TO BE SOLVED: To provide a graphene transistor having an air gap, a hybrid transistor including the same, and a manufacturing method for the same.SOLUTION: A graphene transistor includes: a gate electrode on a substrate; a gate insulation layer on the gate electrode; a graphene channel on the gate insulation layer; a source electrode and a drain electrode separated from each other on the graphene channel; and a cover covering upper surfaces of the source electrode and the drain electrode and forming an air gap between the source electrode and the drain electrode on the graphene channel. The length of the graphene channel between the source electrode and the drain electrode is 10 nm to 100 nm.
摘要翻译：要解决的问题：为了提供一种具有气隙的石墨烯晶体管，包括该石墨烯晶体管的制造方法及其制造方法。石墨烯晶体管包括：基板上的栅电极; 栅电极上的栅极绝缘层; 栅极绝缘层上的石墨烯通道; 在石墨烯通道上彼此分离的源电极和漏电极; 以及覆盖源电极和漏电极的上表面并在石墨烯通道上的源电极和漏电极之间形成气隙的盖。源电极和漏电极之间的石墨烯通道的长度为10nm至100nm。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2011118399A Optical device and method of manufacturing the same 审中-公开
标题翻译：光学装置及其制造方法
公开(公告)号：JP2011118399A
公开(公告)日：2011-06-16
申请号：JP2010270451
申请日：2010-12-03
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： JI HO-CHUL , KIM KI-NAM , HYUNG YONG-WOO , RA KEIEN , HA KYOUNG-HO , PARK YOON-DONG , BAE DAE LOK , BOK JIN-KWON , KANG PIL KYU
IPC分类号： G02B6/122 , G02B6/12 , G02B6/13 , H01L21/205
CPC分类号： G02B6/124 , G02B6/122 , G02B6/30 , G02B6/34 , G02B6/4214 , G02B2006/12104
摘要： PROBLEM TO BE SOLVED: To provide an optical device including an optical waveguide and an optical coupler integrated into a bulk semiconductor substrate on which other circuitry is also integrated, and to provide a method of manufacturing the optical device. SOLUTION: The optical waveguide and a coupler device, and methods of manufacturing them are obtained by: forming a trench in the bulk semiconductor substrate, for example, a bulk silicon substrate; forming a bottom cladding layer in the trench; and forming a core region on the bottom cladding layer. A reflective element, such as a distributed Bragg reflector, can be formed under the coupler and/or the optical waveguide. These optical devices can be integrated into other semiconductor circuits, for example, in a DRAM memory circuit chip on a chip or a substrate in accordance with silicone photonics technology. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括光波导和集成在其中还集成有其他电路的体半导体衬底中的光耦合器的光学器件，并且提供一种制造光学器件的方法。解决方案：光波导和耦合器件及其制造方法通过以下方式获得：在体半导体衬底中形成例如体硅衬底的沟槽; 在沟槽中形成底部包层; 并在下包层上形成芯区。可以在耦合器和/或光波导下形成反射元件，例如分布式布拉格反射器。这些光学器件可以根据硅酮光子学技术集成到其它半导体电路中，例如在芯片或基板上的DRAM存储器电路芯片中。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2008108418A Flash memory device and method of programming multi-pages in the same 审中-公开
标题翻译：闪存存储器件及其编程方法
公开(公告)号：JP2008108418A
公开(公告)日：2008-05-08
申请号：JP2007275333
申请日：2007-10-23
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK KI-TAE , KIM KI-NAM , LEE YEONG-TAEK
IPC分类号： G11C16/02
CPC分类号： G11C16/10 , G11C16/0483 , G11C2216/14
摘要： PROBLEM TO BE SOLVED: To provide a flash memory device and a method of programming multi-pages in the same.
SOLUTION: In programming multi-pages in a flash memory device, a first page group and a second page group are formed with respect to each of at least one memory plane by grouping page buffers such that logical odd bitlines and logical even bitlines correspond to one of the first page group and the second page group, respectively. Program data corresponding to at least one page coupled to a selected wordline are loaded, and then a program voltage is applied to the selected wordline. A plurality of pages, including at least two pages pertaining to the same memory plane, can be simultaneously programmed and a row-coupling disturbance can be reduced.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种闪存器件和一种编程多页的方法。解决方案：在对闪存设备中的多页进行编程中，通过对页缓冲器进行分组来形成关于至少一个存储器平面中的每一个的第一页组和第二页组，使得逻辑奇位图和逻辑偶位分别对应于第一页组和第二页组之一。加载对应于耦合到所选字线的至少一个页面的程序数据，然后将程序电压施加到所选择的字线。包括属于相同存储器平面的至少两页的多个页面可以被同时编程，并且可以减少行耦合干扰。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007318138A Method of operating non-volatile memory device 审中-公开
标题翻译：操作非易失性存储器件的方法
公开(公告)号：JP2007318138A
公开(公告)日：2007-12-06
申请号：JP2007134668
申请日：2007-05-21
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： KIN DAIMAN , KWON WOOK-HYUN , KIM KI-NAM , PARK CHAN-KWANG , SHIM SANG-PIL
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0483 , G11C16/3409 , G11C16/345
摘要： PROBLEM TO BE SOLVED: To provide a method of operating a non-volatile memory device which can decrease the number of electrons stored in a tunnel insulating film, while writing/erasing cycles are repeated. SOLUTION: The method of operating the non-volatile memory device having a memory cell includes a source region 12 and a drain region formed in a semiconductor substrate 10 to define a channel region therebetween, a tunnel insulating layer 16 laminated on the channel region, a charge storing layer 18, and a control gate electrode 22. The method has the steps of: applying a negative voltage to the gate electrode, applying a positive voltage to at least one of the source and drain regions, implanting a hole into the tunnel insulating layer, and recombining the hole injected in the tunnel insulating layer with a negative charge trapped in the tunnel insulating layer, thereby removing the negative charge in the tunnel insulating layer. Thus, by removing the electrons trapped in the tunnel insulating layer, the number of the electrons stored in the tunnel insulating layer during writing/erasing cycles can be significantly decreased, which attains a high reliability with little data variation. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种操作非易失性存储器件的方法，其可以减少存储在隧道绝缘膜中的电子数量，同时重复写/擦除周期。解决方案：具有存储单元的非挥发性存储器件的操作方法包括形成在半导体衬底10中的源区12和漏区，以限定它们之间的沟道区，层叠在沟道上的隧道绝缘层16 区域，电荷存储层18和控制栅电极22.该方法具有以下步骤：向栅电极施加负电压，向源区和漏区中的至少一个施加正电压，将孔注入将隧道绝缘层中注入的空穴与隧道绝缘层中俘获的负电荷重新组合，从而去除隧道绝缘层中的负电荷。因此，通过去除俘获在隧道绝缘层中的电子，可以显着地减少在写入/擦除周期期间存储在隧道绝缘层中的电子数，从而在数据变化很小的情况下获得高的可靠性。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2008166819A Method for forming nonvolatile memory element 审中-公开
标题翻译：形成非易失性存储元件的方法
公开(公告)号：JP2008166819A
公开(公告)日：2008-07-17
申请号：JP2007339979
申请日：2007-12-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： SIM JAE-HWANG , YIM YONG-SIK , KIM KI-NAM , PARK JAE-KWAN
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S438/954
摘要： PROBLEM TO BE SOLVED: To provide a method for forming an NAND-type flash memory nonvolatile memory element which can reduce the dispersion of cell characteristics. SOLUTION: After first mask patterns 120d, 120c, and 120s are arranged at large intervals, interval adjustment films 130 are formed so as to be conformal. Second mask patterns 140c and 140g are formed to fill grooves 132 and 134 that are defined among the first mask pattern 120d, 120c, and 120s, respectively, by the interval adjustment films 130. Accordingly, a grounding selective gate line 140g, a cell gate line 140c and a string select gate line 120s can be formed so that all of these are arranged at equal intervals. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以减少电池特性分散的NAND型闪速存储器非易失性存储元件的形成方法。解决方案：在以大间隔布置第一掩模图案120d，120c和120s之后，形成间隔调整膜130以使其保形。形成第二掩模图案140c和140g以分别通过间隔调整膜130填充在第一掩模图案120d，120c和120s之间限定的槽132和134.因此，接地选择栅极线140g，单元栅极线140c和串选择栅极线120s可以形成为使得所有这些都以相等的间隔布置。版权所有（C）2008，JPO＆INPIT

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