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1. 发明专利

JP2007049143A Dual gate structure and its manufacturing method, and semiconductor device with dual gate structure and its manufacturing method 审中-公开
标题翻译：双门结构及其制造方法及具有双门结构的半导体器件及其制造方法
公开(公告)号：JP2007049143A
公开(公告)日：2007-02-22
申请号：JP2006211298
申请日：2006-08-02
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK HEE-SOOK , LEE JANG-HEE , PARK JAE-HWA , LEE BYUNG HAK , CHA TAEHO , LIM DONG-CHAN , SEONG GEUMJUNG
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a dual gate structure and its manufacturing method, and to provide a semiconductor device with dual gate structure and its manufacturing method.
SOLUTION: The semiconductor device has at least two stacked gate structures formed on the substrate. The two stacked gate structures each has a semiconductor layer and a metal layer formed on the semiconductor layer. The two stacked gate structures formed on the board have intermediate layers which are different from each other. One of the two stacked gate structures has an ohmic layer while the other structure does not.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供双栅极结构及其制造方法，并提供具有双栅极结构的半导体器件及其制造方法。解决方案：半导体器件具有形成在衬底上的至少两个堆叠栅极结构。两个堆叠的栅极结构各自具有形成在半导体层上的半导体层和金属层。形成在板上的两个堆叠的栅极结构具有彼此不同的中间层。两个堆叠的栅极结构中的一个具有欧姆层，而另一个结构不具有欧姆层。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2012009847A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012009847A
公开(公告)日：2012-01-12
申请号：JP2011113410
申请日：2011-05-20
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： MOON GWANG-JIN , PARK BEONG-RYUL , LIM DONG-CHAN , JEONG DOK-YONG , CHOE GIL-HYON , PE TWE-ROK , KANG BI-GYU
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/822 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04 , H01L27/10
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/528 , H01L2224/16146 , H01L2225/06541 , H01L2924/01327 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a via structure and a conductive structure of a semiconductor device.SOLUTION: The via structure includes a front face having a flat part and a protruding part. The conductive structure is formed on at least a part of the flat part but not formed on at least a part of the protruding part. For example, the conductive structure is formed only on the flat part and is not formed on the protruding part. Accordingly, connection of high quality is formed between the conductive structure and the via structure.
摘要翻译：要解决的问题：提供半导体器件的通孔结构和导电结构。解决方案：通孔结构包括具有平坦部分和突出部分的前表面。导电结构形成在平坦部分的至少一部分上，但不形成在突出部分的至少一部分上。例如，导电结构仅形成在平坦部分上，并且不形成在突出部分上。因此，在导电结构和通孔结构之间形成高质量的连接。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2013118373A Electrode connecting structure containing copper 有权
标题翻译：电极连接结构铜
公开(公告)号：JP2013118373A
公开(公告)日：2013-06-13
申请号：JP2012259541
申请日：2012-11-28
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK KENSO , PARK BEONG-RYUL , KIM SU-KYOUNG , MOON GWANG-JIN , BANG SUK-CHUL , LEE DO-SUN , LIM DONG-CHAN , CHOE GIL-HYON
IPC分类号： H01L25/065 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/522 , H01L25/07 , H01L25/18
CPC分类号： H01L24/28 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L25/0655 , H01L2224/05009 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05547 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05647 , H01L2224/08147 , H01L2224/08148 , H01L2224/0903 , H01L2224/8001 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/15787 , H01L2924/15788 , H01L2924/00012 , H01L2224/05552 , H01L2924/00 , H01L2924/04941 , H01L2924/04953
摘要： PROBLEM TO BE SOLVED: To provide an electrode connecting structure containing copper.SOLUTION: An electrode connecting structure or a semiconductor element includes: a lower element which includes a lower substrate, a lower insulating layer formed on the lower substrate and a lower electrode structure formed in the lower insulating layer, and in which the lower electrode structure includes a lower electrode barrier layer and a lower metal electrode formed on the lower electrode barrier layer; and an upper element which includes an upper substrate, an upper insulating layer formed below the upper substrate and an upper electrode structure formed in the upper insulating layer, and in which the lower electrode structure includes an upper electrode barrier layer extending from the inside of the upper insulating layer below a lower surface and an upper metal electrode formed on the upper electrode barrier layer. The lower metal electrode and the upper metal electrode are brought into direct contact with each other.
摘要翻译：要解决的问题：提供一种包含铜的电极连接结构。解决方案：电极连接结构或半导体元件包括：下部元件，其包括下基板，形成在下基板上的下绝缘层和形成在下绝缘层中的下电极结构，并且其中下电极结构包括形成在下电极阻挡层上的下电极阻挡层和下金属电极; 以及上部元件，其包括上基板，形成在所述上基板下方的上绝缘层和形成在所述上绝缘层中的上电极结构，并且其中所述下电极结构包括从所述上绝缘层的内侧延伸的上电极阻挡层位于下表面下方的上绝缘层和形成在上电极阻挡层上的上金属电极。下部金属电极和上部金属电极彼此直接接触。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2006310842A Semiconductor device having polymetal gate electrode and manufacturing method therefor 审中-公开
标题翻译：具有聚合物电极的半导体器件及其制造方法
公开(公告)号：JP2006310842A
公开(公告)日：2006-11-09
申请号：JP2006113558
申请日：2006-04-17
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE BYUNG HAK , LIM DONG-CHAN , CHOI GIL-HEYUN , PARK HEE-SOOK
IPC分类号： H01L29/78 , H01L29/423 , H01L29/49
CPC分类号： H01L21/28061 , H01L27/10873 , H01L27/10891 , H01L29/4933 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a polymetal gate electrode that is provided with a barrier film formed from a TiN film and a buffer layer, and to provide its manufacturing method.
SOLUTION: This is a semiconductor device having a gate insulating film formed on a semiconductor substrate, a conductive polysilicon film laminated on the gate insulating film in order from the semiconductor substrate's side, a first metal silicide film, a barrier film, and a polymetal gate electrode formed from a metal film. The barrier film has the TiN film formed on the first metal silicide film and the buffer layer provided between the TiN film and the metal film.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其具有设置有由TiN膜和缓冲层形成的阻挡膜的多金属栅电极，并提供其制造方法。解决方案：这是一种半导体器件，其具有形成在半导体衬底上的栅极绝缘膜，从半导体衬底侧依次叠层在栅极绝缘膜上的导电多晶硅膜，第一金属硅化物膜，阻挡膜和由金属膜形成的多金属栅电极。阻挡膜具有形成在第一金属硅化物膜上的TiN膜和设置在TiN膜和金属膜之间的缓冲层。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006086525A Semiconductor device and method of manufacturing it 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006086525A
公开(公告)日：2006-03-30
申请号：JP2005261224
申请日：2005-09-08
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： IN SENHITSU , LEE SHOGEN , SOHN WOONG-HEE , CHOI GIL-HEYUN , LEE BYUNG HAK , PARK HEE-SOOK , YOO JONG-RYEOL , LIM DONG-CHAN , PARK JAE-HWA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/105 , H01L27/1052 , H01L27/11546
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing it, and more specifically, a flash memory device and a method of manufacturing it, in which, even if time passes once it data are inputted, that state is maintained and electrical input and output of the data are made possible. SOLUTION: In the flash memory device and the method of manufacturing it, a tunnel oxide film, a floating gate, and a dielectric film which comprises a thin film made of a material with high dielectric constant are formed on a cell region of a semiconductor substrate. A polysilicon film doped with p-type dopant, and a control gate which comprises a conductive film made of a metal material are formed on the dielectric film. The semiconductor substrate, a tunnel oxide film, a polysilicon film pattern which is made of the same material as the floating gate, and a conductive film pattern which is the same as the conductive film are formed on a peripheral circuit region of the semiconductor substrate. Accordingly, even if a simple process is carried out, coupling ratio is improved without generating faults. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种半导体器件及其制造方法，更具体地，涉及一种闪存器件及其制造方法，其中即使在数据输入时经过一次，该状态保持数据的电输入和输出成为可能。解决方案：在闪速存储器件及其制造方法中，包括由具有高介电常数的材料制成的薄膜的隧道氧化物膜，浮动栅极和电介质膜形成在半导体衬底。掺杂有p型掺杂剂的多晶硅膜和由金属材料制成的导电膜的控制栅极形成在电介质膜上。在半导体衬底的外围电路区域上形成半导体衬底，隧道氧化物膜，与浮动栅极相同的材料制成的多晶硅膜图案和与导电膜相同的导电膜图案。因此，即使进行简单的处理，也不会产生故障而提高耦合比。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2013102219A Manufacturing method for semiconductor device having polymetal gate electrode 有权
标题翻译：具有聚合物电极的半导体器件的制造方法
公开(公告)号：JP2013102219A
公开(公告)日：2013-05-23
申请号：JP2013018318
申请日：2013-02-01
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE BYUNG HAK , LIM DONG-CHAN , CHOE GIL-HYON , PARK HEE-SOOK
IPC分类号： H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/28061 , H01L27/10873 , H01L27/10891 , H01L29/4933 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a polymetal gate electrode comprising a barrier film formed from a TiN film and a buffer layer, and to provide a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device comprises: a gate insulating film formed on a semiconductor substrate; and a polymetal gate electrode including a conductive polysilicon film, a first metal silicide film, a barrier film, and a metal film which are laminated on the gate insulating film in order from the semiconductor substrate side. The barrier film comprises: a TiN film formed on the first metal silicide film; and a buffer layer provided between the TiN film and the metal film.
摘要翻译：解决的问题：提供一种半导体器件，其具有包括由TiN膜和缓冲层形成的阻挡膜的多金属栅电极，并提供半导体器件的制造方法。解决方案：半导体器件包括：形成在半导体衬底上的栅绝缘膜; 以及包含导电多晶硅膜，第一金属硅化物膜，阻挡膜和金属膜的多金属栅极电极，其从半导体衬底侧开始依次层压在栅极绝缘膜上。阻挡膜包括：形成在第一金属硅化物膜上的TiN膜; 以及设置在TiN膜和金属膜之间的缓冲层。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2012119689A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2012119689A
公开(公告)日：2012-06-21
申请号：JP2011264735
申请日：2011-12-02
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： PARK BEONG-RYUL , SAI KICHIGEN , BANG SEOK-CHOL , MOON KWANG-JIN , LIM DONG-CHAN , JUNG DUK YOUNG
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/3128 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2221/68327 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/036 , H01L2224/0401 , H01L2224/05009 , H01L2224/05018 , H01L2224/05556 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/05609 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/01029 , H01L2924/01327 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2224/05655 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method in which a misalignment problem with wiring of an upper wiring layer does not arise when forming an opening for a through electrode.SOLUTION: A semiconductor device manufacturing method includes a step of preparing a substrate having a first surface and a second surface on the opposite side of the first surface, a step of forming a sacrifice film pattern on a region in which a through electrode extending from the first surface of the substrate in a thickness direction of the substrate is to be formed, a step of forming an upper wiring layer which is formed on the first surface of the substrate and has wiring located on the sacrifice film pattern, a step of exposing the sacrifice film pattern by partially removing the second surface of the substrate, a step of forming an opening which exposes the wiring by removing the sacrifice film pattern from the second surface of the substrate and a step of forming, in the opening, the through electrode electrically connected with the wiring.
摘要翻译：要解决的问题：提供一种半导体器件制造方法，其中当形成通孔的开口时，不会出现上布线层的布线的不对准问题。解决方案：半导体器件制造方法包括制备在第一表面的相对侧上具有第一表面和第二表面的衬底的步骤，在通孔电极的区域上形成牺牲膜图案的步骤在衬底的厚度方向上从衬底的第一表面延伸的步骤;形成在衬底的第一表面上并具有位于牺牲膜图案上的布线的上部布线层的步骤;步骤通过部分去除基板的第二表面来曝光牺牲膜图案;通过从基板的第二表面去除牺牲膜图案形成露出布线的开口的步骤，以及在开口中形成牺牲膜图案的步骤，通过电极与布线电连接。版权所有（C）2012，JPO＆INPIT

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