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    • 1. 发明专利
    • COMMUNICATION CONTROL SYSTEM AND COMMUNICATION CONTROL METHOD
    • JP2002044183A
    • 2002-02-08
    • JP2000220905
    • 2000-07-21
    • SONY CORP
    • ONUKI ATSUSHIMITSUMA NOBUTAKAYAMAMOTO TSUTOMU
    • G06F13/38G06F13/00H04L1/00H04L29/02H04L29/10
    • PROBLEM TO BE SOLVED: To provide a communication control system that can relieve a load of a CPU of a device to be controlled in a transmission system or the like, adopting the 'Sony disk 9-pin protocol'. SOLUTION: An AV server 30 is provided with a serial communication I/F 1 having a storage means 1a for temporarily storing a prescribed number of character strings sent from a transmission means, a detection means 2 which detects whether or not the interval between characters sent from the transmission means is a time to be judged as a communication error or over, and with a reception means 3 that receives the character string via the I/F 1. The I/F 1 applies 1st interruption to the reception means 3 every time the storage means 1a stores the characters. When the detection means 2 detects that the interval is a time to be judged as the communication error or over, the detection means 2 applies 2nd interruption to the reception means 3. The reception means 3 receives characters of the character string on the basis of the 1st interruption and judges whether or not the reception of all the character string is finished, and judges the presence of a communication error on the basis of the 2nd interruption.
    • 9. 发明专利
    • CONVERGENCE CORRECTION CIRCUIT
    • JPH08154255A
    • 1996-06-11
    • JP29410294
    • 1994-11-29
    • SONY CORP
    • YAMAMOTO TSUTOMUMURAYAMA YUTAKA
    • H04N9/28H04N3/26
    • PURPOSE: To attain stable and accurate convergence correction when plural different horizontal deflection frequencies are received. CONSTITUTION: The correction circuit is provided with a retrace width reduction circuit 1 outputting a processing horizontal timing signal reduced with the retrace period of a horizontal timing signal and with a convergence correction reference waveform generating circuit 2 generating a convergence reference waveform signal synchronously with the processing horizontal timing signal, and also with a trace start and level detection circuit 3 detecting a voltage level of a convergence correction reference waveform signal at the start and end point of time of the trace period of the horizontal timing signal and a comparator 4 comparing the detection voltage level with a reference voltage level from a reference voltage generating section 5. Then a comparison output of the comparator 4 is fed back to the convergence correction reference waveform generating circuit 2.