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1. 发明专利

JP2005005435A Mounting substrate and its manufacturing method 审中-公开
标题翻译：安装基板及其制造方法
公开(公告)号：JP2005005435A
公开(公告)日：2005-01-06
申请号：JP2003166347
申请日：2003-06-11
申请人： Sony Corp , ソニー株式会社
发明人： INOYAE HIDEKO , ORUI KEN , NISHITANI YUJI , KUSANO HIDETOSHI , ASAMI HIROSHI
IPC分类号： H05K3/28 , H01L23/12 , H05K1/14 , H05K1/18 , H05K3/20
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a thin mounting substrate also having excellent dimensional stability, and a manufacturing method for the substrate. SOLUTION: The mounting substrate has a process in which a conductor pattern 12 is formed on one surface of a transfer sheet 10, a process in which an air gap 16 is formed at an insulating layer 14, a process in which the sheet 10 and the layer 14 are laminated with each other so as to hold the pattern 12 and the sheet 10 is removed, a process in which an element 17 is housed in the air gap 16 while being electrically connected to the pattern 12, and a process in which external terminals 22 electrically connected to the element 17 are joined with the reverse surface of the connecting surface of the element 17 in the pattern 12. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有优异的尺寸稳定性的薄的安装基板以及用于基板的制造方法。解决方案：安装基板具有在转印纸10的一个表面上形成导体图案12的工艺，其中在绝缘层14处形成气隙16的工艺，其中片材 10并且层14彼此层叠以便保持图案12并且去除片材10，其中元件17容纳在气隙16中同时电连接到图案12的过程，以及处理其中电连接到元件17的外部端子22以图案12与元件17的连接表面的相反表面接合。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2008047710A Semiconductor substrate and semiconductor device, and manufacturing method thereof 审中-公开
标题翻译：半导体衬底和半导体器件及其制造方法
公开(公告)号：JP2008047710A
公开(公告)日：2008-02-28
申请号：JP2006222053
申请日：2006-08-16
申请人： Sony Computer Entertainment Inc , Sony Corp , ソニー株式会社 , 株式会社ソニー・コンピュータエンタテインメント
发明人： NISHITANI YUJI , OIDE TOMOSHI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To obtain a coreless semiconductor substrate further readily without damaging reliability.
SOLUTION: After a multilayer wiring which enables a semiconductor chip to be mounted on a base metallic substrate 100 is constructed in a plurality of regions, a part of the metallic substrate 100 is selectively etched by using a resist, and a stiffener 160 is formed to enclose an electrode pad 25 in each semiconductor chip mounting region. Each region is cut by dicing processing or the like, and a semiconductor substrate 11 with the stiffener 160 is subjected to discrete dicing treatment.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：进一步获得无芯半导体衬底而不损害可靠性。解决方案：在多个区域中构成能够将半导体芯片安装在基底金属基板100上的多层布线之后，通过使用抗蚀剂选择性地蚀刻金属基板100的一部分，并且加强件160 形成为在每个半导体芯片安装区域中包围电极焊盘25。通过切割处理等切割每个区域，并且对具有加强件160的半导体基板11进行离散的切割处理。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007335740A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007335740A
公开(公告)日：2007-12-27
申请号：JP2006167624
申请日：2006-06-16
申请人： Sony Computer Entertainment Inc , Sony Corp , ソニー株式会社 , 株式会社ソニー・コンピュータエンタテインメント
发明人： KANAYAMA FUJIO , OIDE TOMOSHI , ADACHI MITSURU , NISHITANI YUJI , NIIMI TETSUNAGA , KUSANO HIDETOSHI , SASAKI ATSUO
IPC分类号： H01L23/28 , H01L23/29 , H01L23/31
CPC分类号： H01L2224/16225 , H01L2924/15311 , H01L2924/19106
摘要： PROBLEM TO BE SOLVED: To protect a semiconductor chip in a semiconductor device properly, and to suppress influences received from an environment surrounding the semiconductor chip. SOLUTION: The semiconductor device 10 comprises an underfill 70 charging a gap between a substrate 20 and a semiconductor chip 30, and a sealing resin layer 40 covering a part of the substrate 20. The sealing resin layer 40 has a sealing part 40a for sealing a side face 30a of the semiconductor chip 30 through the underfill 70 projecting to the side face 30a, so that a rear face of the semiconductor chip 30 is exposed from the sealing resin layer 40; and a recess 40c which is provided in the upper region of the underfill 70 projecting to the side face 30a, and is lower than the upper face 40b of the sealing resin layer 40. Thus, a force is decreased in which a filet 70a receives from the sealing resin layer 40, and it is possible to suppress a peeling of the filet 70a contained in the underfill 70 from the semiconductor chip 30. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：适当地保护半导体器件中的半导体芯片，并且抑制从半导体芯片周围的环境接收的影响。解决方案：半导体器件10包括填充衬底20和半导体芯片30之间的间隙的底部填充物70以及覆盖衬底20的一部分的密封树脂层40.密封树脂层40具有密封部40a 用于通过向侧面30a突出的底部填充物70密封半导体芯片30的侧面30a，使得半导体芯片30的背面从密封树脂层40露出; 以及凹部40c，其设置在向侧面30a突出的底部填充物70的上部区域中，并且比密封树脂层40的上表面40b低。因此，压片70a从密封树脂层40，并且可以抑制来自半导体芯片30的底部填充物70中包含的file口70a的剥离。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2006032753A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006032753A
公开(公告)日：2006-02-02
申请号：JP2004211143
申请日：2004-07-20
申请人： Sony Corp , ソニー株式会社
发明人： HATANO MASAKI , ASAMI HIROSHI , NISHITANI YUJI
IPC分类号： H01L23/12 , H01L25/00 , H01L31/02 , H01S5/026
CPC分类号： H01L2224/12105 , H01L2224/19 , H01L2224/24 , H01L2224/73267 , H01L2224/92244 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To suppress deterioration of high frequency characteristics of a high frequency device, and to realize a reduced optical loss of an optical element, by providing a sacrifice film on desired regions of the device or the optical element, and by removing the sacrifice film after forming an insulation film.
SOLUTION: The semiconductor device manufacturing method comprises steps of: mounting a device 21 and optical element 31 on a substrate (interposer substrate 11); forming a sacrifice film 41 on desired regions of the device 21 and the optical element 31; forming an insulation film 16 covering the device 21 and the optical element 31 together with the sacrifice film 41; forming an opening 17 in the insulation film 16 on the sacrifice film 41; and removing the sacrifice film 41 through the opening 17. The semiconductor device 1 is manufactured by this method.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过在器件或光学元件的期望区域上提供牺牲膜，抑制高频器件的高频特性的劣化，并实现光学元件的光损耗的降低，以及通过在形成绝缘膜之后去除牺牲膜。解决方案：半导体器件制造方法包括以下步骤：将器件21和光学元件31安装在衬底（插入器衬底11）上; 在装置21和光学元件31的所需区域上形成牺牲膜41; 与牺牲膜41一起形成覆盖装置21和光学元件31的绝缘膜16; 在牺牲膜41上的绝缘膜16中形成开口17; 并且通过开口17去除牺牲膜41.通过该方法制造半导体器件1。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005303021A Wiring substrate, semiconductor device and manufacturing method thereof 有权
标题翻译：接线基板，半导体器件及其制造方法
公开(公告)号：JP2005303021A
公开(公告)日：2005-10-27
申请号：JP2004117458
申请日：2004-04-13
申请人： Sony Corp , ソニー株式会社
发明人： ORUI KEN , ASAMI HIROSHI , NISHITANI YUJI
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate and a semiconductor device which are capable of formation of a highly reliable solder connection part at a low cost and well correspond to a large sized IC chip, IC multi-pin design and package miniaturization; and to provide a manufacturing method thereof. SOLUTION: A solder connection for junction between the connection land 22 of a wiring substrate 20 and an electrode pad 37 of an IC chip 36 is constituted of a projection electrode 30 having a stress relaxing layer 26 formed of a resin inside. The projection electrode 30 is formed in the wiring substrate 20 side, and is constituted of a first connection part 30A closing an opening 24a for opening the connection land 22, and a second connection part 30B formed on an insulating layer 24 with a larger diameter than the first connection part 30A. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供能够以低成本形成高可靠性焊接部分的布线基板和半导体器件，并且很好地对应于大尺寸IC芯片，IC多引脚设计和封装小型化; 并提供其制造方法。解决方案：布线基板20的连接台面22与IC芯片36的电极焊盘37之间的接合点的焊接连接部由具有由树脂内部形成的应力缓和层26的突起电极30构成。突起电极30形成在布线基板20侧，并且由封闭用于打开连接台面22的开口24a的第一连接部30A和形成在直径比直径大的绝缘层24上的第二连接部30B 第一连接部30A。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005259925A Mounting method 审中-公开
标题翻译：安装方法
公开(公告)号：JP2005259925A
公开(公告)日：2005-09-22
申请号：JP2004068483
申请日：2004-03-11
申请人： Sony Corp , ソニー株式会社
发明人： HAYAKAWA HISASHI , NISHITANI YUJI , ASAMI HIROSHI
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L24/75 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/83192 , H01L2924/00011 , H01L2924/01322 , H01L2924/14 , H01L2924/00 , H01L2224/81805
摘要： PROBLEM TO BE SOLVED: To provide the mounting method of a chip-shaped electronic component, capable of high reliability junction by restraining the production of an alloy due to intermetallic diffusion. SOLUTION: Before a solder ball 14, formed on the side of an IC chip 10, makes contact with the wiring land 2 of a substrate 1, the solder ball 14 is heated beyond a melting point and melted, and is brought into contact with the wiring land 2 in the molten state. The molten state is kept after the contacting, and then heating is stopped and cooling is applied. Consequently, since jointing time is shortened to restrain alloy formation and proper jointing is made. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供能够通过抑制由金属间扩散产生合金而能够实现高可靠性接合的芯片形电子部件的安装方法。解决方案：在形成在IC芯片10侧的焊球14与基板1的布线台2接触之前，将焊球14加热超过熔点并熔融，在熔融状态下与布线区域2接触。在接触之后保持熔融状态，然后停止加热并施加冷却。因此，由于缩短接合时间以抑制合金的形成并进行适当的接合。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2003298232A Multilayer wiring board and method of manufacturing the same 审中-公开
标题翻译：多层接线板及其制造方法
公开(公告)号：JP2003298232A
公开(公告)日：2003-10-17
申请号：JP2002099883
申请日：2002-04-02
申请人： Sony Corp , ソニー株式会社
发明人： ASAMI HIROSHI , KUSANO HIDETOSHI , NISHITANI YUJI , ORUI KEN
IPC分类号： H05K3/22 , H01L23/12 , H05K3/00 , H05K3/20 , H05K3/46
CPC分类号： H05K3/4694 , H01L21/4846 , H01L21/4857 , H01L23/49833 , H01L2924/0002 , H01L2924/09701 , H05K3/0023 , H05K3/205 , H05K3/4617 , H05K3/4623 , H05K2201/0195 , H05K2201/09536 , H05K2201/09881 , H05K2201/09972 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board, which is capable of ensuring dimensional stability for a conductor pattern formed at a fine pitch, removing limitations imposed on processes as for the selection of materials, and reducing a production cost and to provide the multilayer wiring board. SOLUTION: A second wiring board 22 and an adhesive material layer 23 formed on a metal support sheet 40 are partially laminated on a prescribed region of a first wiring board 21 by the use of the support sheet 40. After the second wiring board 22 is laminated, lastly the support sheet 40 is removed by etching. The second wiring board 22 is laminated only on a part of the first wiring board 21 which is required to get multilayered so as to reduce the amount of component materials used for the second wiring board. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种制造多层布线板的方法，其能够确保以细间距形成的导体图案的尺寸稳定性，消除对于材料选择的过程的限制，并且减少生产成本并提供多层布线板。解决方案：通过使用支撑片40，在金属支撑片40上形成的第二布线板22和粘合材料层23部分地层压在第一布线板21的规定区域上。在第二布线板 22层压，最后通过蚀刻去除支撑片40。第二布线基板22仅层叠在需要多层化的第一布线基板21的一部分上，以减少用于第二布线基板的部件材料的量。版权所有（C）2004，JPO

8. 发明专利

JP2000133664A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000133664A
公开(公告)日：2000-05-12
申请号：JP30049498
申请日：1998-10-22
申请人： SONY CORP
发明人： NISHITANI YUJI
IPC分类号： H01L23/12 , H01L21/56 , H01L21/60 , H01L23/28
摘要： PROBLEM TO BE SOLVED: To improve the reliability of the connection in face-down mounting of a semiconductor element with resin. SOLUTION: This a semiconductor device is provided with a through hole (h) penetrating from the front surface through the rear surface of a substrate 1, a wiring pattern 2 formed in the vicinity of the through hole (h) of the substrate 1, a bump B connected with the wiring pattern 2 electrically and mechanically, and a semiconductor element 3 mounted on the substrate 1 via the bump B. The device is also provided with a resin 4 which is applied onto the wiring pattern 2 except for the inside of the through hole (h) and the part between the through hole (h), and the semiconductor element 3 in order to connect the bump B of the semiconductor element 3 with the wiring pattern 2.

9. 发明专利

JPH09148486A BALL GRID ARRAY PACKAGE TYPE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09148486A
公开(公告)日：1997-06-06
申请号：JP32977295
申请日：1995-11-25
申请人： SONY CORP
发明人： NISHITANI YUJI , TAWARA HIROKI , NOGUCHI MAKOTO , SETO KEIJI
IPC分类号： H01L23/12 , H01L25/00
摘要： PROBLEM TO BE SOLVED: To automatically form coupling material for mounting electronic parts on the face on the opposite side of a package substrate 1 from a ball electrode by screen printing or the like. SOLUTION: A heat sink retaining step 2b is provided on the opposite side of the device ball 2 of a package board 1 from a ball electrode, and a heat sink 5 which has a thickness more than its thickness and on which a semiconductor element 4 is bonded is fixed to it. Hereby, the surface of the heat sink 4 does not project from the surface of the package substrate 1, so coupling material for mounting electronic parts can be made on the surface by, for example, screen printing, and there is no necessity for a worker to form it manually. Accordingly, the productivity improves, and cost can be reduced.

10. 发明专利

JPH06216509A ELECTRONIC COMPONENT 失效
公开(公告)号：JPH06216509A
公开(公告)日：1994-08-05
申请号：JP2054493
申请日：1993-01-12
申请人： SONY CORP
发明人： NISHITANI YUJI
IPC分类号： H05K1/18 , H05K3/28 , H05K3/30 , H05K3/32 , H05K3/34
摘要： PURPOSE:To prevent two lands from being electrically conducted by providing a silver paste heaping part formed of a space of the prescribed capacity between the two lands. CONSTITUTION:A silver paste heaping part 6 formed of a space of the prescribed capacity is provided between two lands 3 whereupon a chip component 10 is to be connected. For example, a protecting film 5 is not provided between the chip component 10 and a substrate 2, a space with a height almost equal to the height of the land 3 is formed and silver paste 4 is permitted to heap in the space. When the capacity of the silver paste heaping part 6 is permitted to be larger than the capacity of the silver paste 4 that fills under the chip component 10, the silver paste is permitted to heap on the side of each land 3 of the silver paste heaping part 6 and the silver paste 4 does not connect inside. Thus, the two lands are prevented from being electrically conducted.

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