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1. 发明专利

JP2011138856A Method of manufacturing semiconductor device and semiconductor device 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：JP2011138856A
公开(公告)日：2011-07-14
申请号：JP2009296749
申请日：2009-12-28
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： FURUKAWA KATSUETSU , NAKAYAMA SATORU , KAMATA SHOGO , KIYOFUJI SHIGEMITSU
IPC分类号： H01L21/304 , H01L21/301 , H01L21/768 , H01L23/522
CPC分类号： H01L21/304 , H01L21/78 , H01L23/585 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/05014 , H01L2224/05095 , H01L2224/05554 , H01L2224/0616 , H01L2924/01019 , H01L2924/14 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent contamination of the principal surface side of a semiconductor wafer in a process of grinding the back surface side of the semiconductor wafer.
SOLUTION: At an intersection of a scribe region 1b of the semiconductor wafer 20 whose back surface side 2b is to be ground, a plurality of insulating layers 3 are laminated over the principal surface 2a in the same manner as an insulating layer (first insulating layer) 3 constituting a wiring layer 5 laminated over a device region 1a. Moreover, in the same layer as wiring (uppermost wiring) formed in the uppermost wiring layer (uppermost wiring layer) 5c disposed at the uppermost layer among the plurality of wiring layers 5 formed for a device region 1a, a metal pattern 10 is formed. Furthermore, an insulating layer (second insulating layer) 9 covering the uppermost wiring is also formed over the metal pattern 10 so as to cover the same.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了防止在研磨半导体晶片的背面侧的过程中半导体晶片的主表面侧的污染。解决方案：在背面2b要被研磨的半导体晶片20的划片区域1b的交点处，以与绝缘层相同的方式在主表面2a上层叠多个绝缘层3 第一绝缘层）3，其构成层叠在器件区域1a上的布线层5。此外，在形成于设置在区域1a的多个布线层5中的最上层布线层（最上布线层）5c中形成的布线（最上布线）的同一层中，形成金属图案10。此外，覆盖最上面布线的绝缘层（第二绝缘层）9也形成在金属图案10上以覆盖其上。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2011123958A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011123958A
公开(公告)日：2011-06-23
申请号：JP2009281288
申请日：2009-12-11
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SHIMAZU KATSUHIRO , NAKAGAWA KOICHI , KAMATA SHOGO , KIYOFUJI SHIGEMITSU
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce the operating voltage of a semiconductor device including a nonvolatile memory. SOLUTION: The semiconductor device includes a nonvolatile memory NVM provided on a silicon substrate 1. Each memory cell MC1 includes an n-channel write transistor QW1 and a capacitor CM1 provided on a memory p-well PW1, and a p-channel erase transistor QE1 provided on a memory n-well NW1. The elements are formed across a memory gate insulating film MI1, and share a portion of a floating gate electrode FG1 in the floating state. The write transistor QW1 is an element that injects electrons into the floating gate electrode FG1 for writing. The capacitor CM1 is an element for controlling the potential of the floating gate electrode FG1. The erase transistor QE1 is an element that extracts electrons of the floating gate electrode FG1 for erasure. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：降低包括非易失性存储器的半导体器件的工作电压。解决方案：半导体器件包括设置在硅衬底1上的非易失性存储器NVM。每个存储单元MC1包括设置在存储器p阱PW1上的n沟道写入晶体管QW1和电容器CM1，以及p沟道擦除晶体管QE1，设置在存储器n阱NW1上。这些元件跨越存储器栅极绝缘膜MI1形成，并且在浮置状态下共享浮置栅极电极FG1的一部分。写入晶体管QW1是将电子注入用于写入的浮置栅极电极FG1的元件。电容器CM1是用于控制浮栅电极FG1的电位的元件。擦除晶体管QE1是提取用于擦除的浮栅电极FG1的电子的元件。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2014060415A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014060415A
公开(公告)日：2014-04-03
申请号：JP2013223610
申请日：2013-10-28
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： FURUKAWA KATSUETSU , NAKAYAMA SATORU , KAMATA SHOGO , KIYOFUJI SHIGEMITSU
IPC分类号： H01L21/301 , H01L21/3205 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To prevent contamination of a principal surface side of a semiconductor wafer in a process for grinding a back surface side of the semiconductor wafer.SOLUTION: At an intersection of a scribe region 1b of a semiconductor wafer 20 whose back surface side 2b is to be ground, a plurality of insulating layers 3 are laminated on a principal surface 2a in the same manner as an insulating layer (a first insulating layer) 3 constituting a wiring layer 5 laminated on a device region 1a. Moreover, in the same layer as wiring (uppermost wiring) formed in the uppermost wiring layer (an uppermost wiring layer) 5c disposed at the uppermost layer among the plurality of wiring layers 5 formed in a device region 1a, a metal pattern 10 is formed. Furthermore, an insulating layer (a second insulating layer) 9 covering the uppermost wiring is also formed on an upper surface of the metal pattern 10 so as to cover the same.
摘要翻译：要解决的问题：为了防止半导体晶片的背面侧的研磨工序中的半导体晶片的主面侧的污染。解决方案：在半导体晶片20的划线区域1b的交叉部分， 2b将被研磨，多个绝缘层3以与构成层叠在器件区域1a上的布线层5的绝缘层（第一绝缘层）3相同的方式层叠在主表面2a上。此外，在形成在设置在设备区域1a中的多个布线层5中的最上层布线层（最上布线层）5c中形成的布线（最上布线）的同一层中，形成金属图案10 。此外，覆盖最上面布线的绝缘层（第二绝缘层）9也形成在金属图案10的上表面上以覆盖其上。

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