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1. 发明专利

JP2012138419A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012138419A
公开(公告)日：2012-07-19
申请号：JP2010288455
申请日：2010-12-24
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： IWASAKI TOSHIFUMI , MOMONO HIROYUKI
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/822 , H01L23/522 , H01L23/532 , H01L27/04
CPC分类号： H01L2224/05
摘要： PROBLEM TO BE SOLVED: To prevent copper wiring in a semiconductor chip from being partially lost.SOLUTION: In a semiconductor device having multilayer interconnection of large area such that an area of lower layer wiring per one upper layer plug is 10000 μmor more, a structure is not formed, in which the multilayer interconnection is connected on a principal surface of a semiconductor substrate 1S to a p-well PW via an n-type diffusion layer NS. In the semiconductor device, are formed a structure in which the multilayer interconnection is connected with the p-well PW via a p-type diffusion layer PS, a structure in which the multilayer interconnection is connected with the n-type diffusion layer NS via the p-type diffusion layer PS, and a structure in which the multilayer interconnection is connected with an n-well via the n-type diffusion layer NS or a structure in which the multilayer interconnection is connected with a gate electrode of MISFET formed on the semiconductor substrate 1S.
摘要翻译：要解决的问题：为了防止半导体芯片中的铜布线部分损失。解决方案：在具有大面积的多层互连的半导体器件中，每个上层插塞的下层布线的面积为10000μm 2 以上，结构为未形成，其中多层互连通过n型扩散层NS连接到半导体衬底1S的主表面到p阱PW。在半导体器件中，形成多层互连通过p型扩散层PS与p阱PW连接的结构，其中多层互连通过n型扩散层NS与n型扩散层NS连接 p型扩散层PS，以及其中多层互连通过n型扩散层NS与n阱连接的结构或其中多层互连与形成在半导体上的MISFET的栅电极连接的结构底物1S。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2014107456A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2014107456A
公开(公告)日：2014-06-09
申请号：JP2012260354
申请日：2012-11-28
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： OGATA KAN , IWASAKI TOSHIFUMI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/823418 , H01L21/823425 , H01L21/823475 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To improve the performance and manufacturing yield of a semiconductor device.SOLUTION: A sidewall spacer SW composed of insulating films IL2, IL3 is formed on a sidewall of a gate electrode GE by etching back the insulating films IL2, IL3 after sequentially forming the insulating films IL2, IL3 so as to cover the gate electrode GE on a semiconductor substrate SB. Then, a source-drain region SD is formed in the semiconductor substrate SB by injecting ions using the gate electrode GE and the wall spacer SW as masks. Then, the thickness of the sidewall spacer SW is reduced by isotropically etching the sidewall spacer SW under a condition where the insulating film IL2 is more hardly etched than the insulating film IL3. Thereafter, a reactive layer formed by reaction between metal and the source-drain region SD is formed in the source-drain region SD.
摘要翻译：要解决的问题：提高半导体器件的性能和制造成品率。解决方案：通过在栅电极GE的侧壁上蚀刻绝缘膜IL2，IL3，形成由绝缘膜IL2，IL3构成的侧壁间隔物SW 依次形成绝缘膜IL2，IL3，以覆盖半导体衬底SB上的栅电极GE。然后，通过使用栅电极GE和壁间隔件SW注入离子作为掩模，在半导体衬底SB中形成源极 - 漏极区域SD。然后，在绝缘膜IL2比绝缘膜IL3几乎不被蚀刻的状态下，通过各向同性蚀刻侧壁间隔物SW来减小侧壁间隔物SW的厚度。此后，在源极 - 漏极区域SD中形成由金属和源极 - 漏极区域SD之间的反应形成的反应层。

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