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1. 发明专利

JP2006074058A Bonding equipment and method of manufacturing semiconductor integrated circuit device 有权
标题翻译：联系设备及制造半导体集成电路设备的方法
公开(公告)号：JP2006074058A
公开(公告)日：2006-03-16
申请号：JP2005279745
申请日：2005-09-27
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： ISHIGURO TAKANORI , HIGUCHI KAZUNORI , SUDA TOMIJI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a bonding technology capable of preventing stripe slip avoiding increase in bonding time, shortening the bonding time, and accurately bonding a chip to a specified position of the carrier.
SOLUTION: In a bonding equipment 10 for bonding a chip 12 onto the specified position of a carrier 1, the chip 12 is arranged on the specified position of a tape carrier 2 by a value specified beforehand such that an inner lead 7 and an electrode pad 14 do not overlap each other, and then bonding is carried out by the rearrangement to the specified position. At the time of the rearrangement, error is looked for by measuring the position of the chip 12 shifted and arranged and rearrangement is carried out onto the position specified such that the error looked for is eliminated.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够防止条纹滑移的接合技术，避免接合时间增加，缩短接合时间，并将芯片精确地接合到载体的指定位置。解决方案：在用于将芯片12接合到载体1的指定位置的接合设备10中，芯片12以预先指定的值布置在带载体2的指定位置上，使得内引线7和电极焊盘14彼此不重叠，然后通过重新布置到指定位置进行结合。在重新布置时，通过测量移位并布置的芯片12的位置并且重新排列进行到指定的位置以便消除寻找的错误，来寻找错误。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005050854A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005050854A
公开(公告)日：2005-02-24
申请号：JP2003202959
申请日：2003-07-29
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： ISHIDA JUNICHI , SUDA TOMIJI , ISHIGURO TAKANORI , KURODA AKIRA , OSAWA HIROYUKI
IPC分类号： H01L21/60 , H01L21/52
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2924/01322 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide clamp mechanism which is easy to manage clamping force. SOLUTION: Equipment which clamps a flexible wiring board 20 at a bonding position, like a COF bonder, and performs bonding by heat crimping is provided with a magnetic path forming unit 46 in an upper clamper 41 and a lower clamper 42 which clamp the flexible wiring board 20. The upper clamper 41 sucks the magnetic path forming unit 46 of the upper clamper 41 side to an electromagnetic force generating unit 52 side which generates electromagnetic force matched with specification of the flexible wiring board 20 by instruction from the equipment main body 51 side, and make the magnetic path forming unit 46 descend on the wiring board 20 on the lower clamper 42. The clamping force is managed by controlling quantitatively the generation electromagnetic force by using electric parameters such as a current and a voltage. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供易于管理夹紧力的夹紧机构。解决方案：在COF接合机的接合位置夹住柔性布线板20并通过热压接进行接合的设备在上夹持器41和下夹持器42中设置有磁路形成单元46，夹持器42夹紧上部夹持器41将上部夹持器41侧的磁路形成单元46吸附到电磁力产生单元52侧，该电磁力产生单元52侧通过来自设备主体的指令产生与柔性布线板20的规格相匹配的电磁力主体51侧，并使磁路形成单元46在下夹持器42上的布线板20上下降。通过使用诸如电流和电压的电参数定量地控制发电电磁力来管理夹紧力。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2006032987A Manufacturing method for bonding equipment and semiconductor ic device 审中-公开
标题翻译：用于连接设备和半导体IC器件的制造方法
公开(公告)号：JP2006032987A
公开(公告)日：2006-02-02
申请号：JP2005279744
申请日：2005-09-27
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： ISHIGURO TAKANORI , HIGUCHI KAZUNORI , SUDA TOMIJI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To prevent the horizontal slippage of carriers, and to shorten the bonding time.
SOLUTION: In bonding equipment 20, where a tape carrier 2 is conveyed by rollers R1-R6 and a chip 12 is bonded at a specified position, the rollers R1-R6 are opened and closed instantaneously, and the horizontal slippages can be prevented by the restoration capability of the tape carrier 2 itself. Slacks are alternately formed between rollers R2 and R3, as well as between R4 and R5 due to the delivery of the tape carrier 2, while the slack on both sides can be dissolved alternately due to the delivery of the tape carrier 2. Since the tape carrier can be delivered at a faster pace when the slack is dissolved, the whole conveying time can be set to be short and a long bonding time can be secured. The chip 12 is supplied to the specified position of the tape carrier 2, after offsetting, and the chip 12 is reset at a regular position after correcting the position, which is performed after the recognition of the electrode pad position of the chip. The bonding of the chip to the carrier can be performed accurately, in a short amount of time.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止载体的水平滑动，并缩短粘合时间。
解决方案：在粘合设备20中，通过辊子R1-R6输送带架2并且在特定位置处接合芯片12，辊子R1-R6立即打开和关闭，并且水平滑动可以通过带载体2自身的恢复能力来防止。由于带式载体2的传送，在辊R2和R3之间以及R4和R5之间交替地形成了松弛，同时由于带式载体2的传送，两侧的松弛可以交替地溶解。由于带当松弛溶解时，载体可以以更快的速度递送，整个输送时间可以设定得短并且可以确保长的粘合时间。芯片12在偏移之后提供给带载器2的指定位置，并且在校正在识别芯片的电极焊盘位置之后执行的位置的情况下将芯片12复位在规则位置。可以在短时间内精确地执行芯片与载体的接合。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2004259866A Manufacturing method for semiconductor device 审中-公开
公开(公告)号：JP2004259866A
公开(公告)日：2004-09-16
申请号：JP2003047551
申请日：2003-02-25
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： ISHIGURO TAKANORI , KODA YUTAKA , KINOSHITA SHIYOUJI , KAWAI MINORU , SHINODA MASAYOSHI , SUDA TOMIJI , ISHIDA JUNICHI , KURODA AKIRA
IPC分类号： H01L21/60
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a bonding technique by which an inner lead can be bonded properly to an electrode pad.
SOLUTION: When a plurality of the inner leads 25 are thermocompression-bonded collectively on a plurality of bumps 15, a touch speed 61 of a bonding tool 51, an initial load applying speed 64, an initial load search speed 65, load change speed 68, a second load search speed 69, a load reducing speed 73, and a second bonding-tool elevating speed 75 are controlled as factors excepting a bonding temperature, a bonding load and a load holding time.
COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2009194234A Methods of manufacturing semiconductor device and semiconductor electronic component, and semiconductor electronic component 审中-公开
标题翻译：制造半导体器件和半导体电子元件的方法和半导体电子元件
公开(公告)号：JP2009194234A
公开(公告)日：2009-08-27
申请号：JP2008035006
申请日：2008-02-15
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ISHIGURO TAKANORI
IPC分类号： H01L21/60 , H01L21/677
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enable an adsorption jig for use in a semiconductor device manufacturing technology to be heat-resistant at 300°C or more. SOLUTION: The adsorption jig such as a collet 60 and the like mounted on a collet holder 61 is provided with high heat resistance. Adoption of such structure as above allows the collet 60 which has so far caused heat deterioration at temperature applied in gold/tin eutectic bonding and the like to be used without causing the heat deterioration and the like. A predetermined high heat resistance silicon resin is preferably used for the high heat resistance. Such a commercial product as FX-T154 can be enumerated as an example. The high heat resistance silicon resin whose Shore A hardness is 10 to 90 is preferably used. Further, proper conductivity may be applied to the high heat resistance silicon resin by adding conductive agent thereto. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了使在半导体器件制造技术中使用的吸附夹具能够在300℃以上耐热。解决方案：安装在夹头保持器61上的诸如夹头60等的吸附夹具具有高耐热性。采用上述结构允许使用迄今为止在使用金/锡共晶接合等的温度下引起热劣化的夹头60而不引起热劣化等。优选使用预定的高耐热性硅树脂来获得高耐热性。像FX-T154这样的商业产品可以列举为例。优选使用肖氏A硬度为10〜90的高耐热性硅树脂。此外，通过向其中加入导电剂可以对高耐热硅树脂施加适当的导电性。版权所有（C）2009，JPO＆INPIT

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