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1. 发明专利

JP2005108980A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005108980A
公开(公告)日：2005-04-21
申请号：JP2003337630
申请日：2003-09-29
申请人： Rohm Co Ltd , ローム株式会社
发明人： HIGASHIDA YOSHIFUMI
IPC分类号： H01L27/04 , H01L21/337 , H01L21/822 , H01L21/8232 , H01L21/8234 , H01L27/02 , H01L27/06 , H01L27/085 , H01L27/088 , H01L27/098 , H01L29/78 , H01L29/808 , H01L21/06
CPC分类号： H01L27/085 , H01L27/0266 , H01L27/098 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve the resistance against electrostatic breakdown, while controlling the increase in chip size. SOLUTION: The semiconductor device is formed by inserting a protection element 2, comprising JFETs 2a, 2b, 2c of polysilicon layers connected in series in the three stages, between a gate electrode G and a source electrode S of a semiconductor device 1 of a power MOSFET or IGBT. Even if a high voltage, such as static electricity is either a positive or a negative polarity, the gate insulating film of the semiconductor active element 3 of the semiconductor device 1 is protected. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以在控制芯片尺寸的增加的同时提高耐静电电击的电阻的半导体器件。解决方案：半导体器件通过在半导体器件1的栅电极G和源电极S之间插入包括三级串联连接的多晶硅层的JFET 2a，2b，2c的保护元件2 的功率MOSFET或IGBT。即使诸如静电之类的高电压是正极性或负极性，半导体器件1的半导体有源元件3的栅极绝缘膜被保护。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004186634A Junction type field effect transistor 审中-公开
标题翻译：连接型场效应晶体管
公开(公告)号：JP2004186634A
公开(公告)日：2004-07-02
申请号：JP2002355014
申请日：2002-12-06
申请人： Rohm Co Ltd , ローム株式会社
发明人： HIGASHIDA YOSHIFUMI
IPC分类号： H01L27/095 , H01L21/337 , H01L29/808
摘要： PROBLEM TO BE SOLVED: To provide a junction FET wherein a trouble that other components are connected with the circuit of its mounted substrate is eliminated, and even when very-high-frequency noise components are inputted to the FET they can be absorbed surely without increasing its circuit area. SOLUTION: The front surface side of a p-type semiconductor substrate 1 has an n-type region 2b to be a diode portion 17 and an n-type well region 2a to be a transistor portion 16. A p-type region 9 is formed in the n-type region 2b of the diode portion. A plurality of gate regions 3 comprising p-type regions are so formed in parallel with each other in the well region 2a that the regions of both the sides of each gate region 3 operate respectively as each source region 5 and each drain region 4. A gate electrode 6, a drain electrode 7, and a source electrode 8 are connected respectively with these respective regions 3, 4, 5. The reverse polarity diode 17 is provided connectively between the gate and source electrodes 6, 8, and a capacitor 11 is provided connectively between the drain and source electrodes 7, 8. COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：为了提供结合FET，其中消除了其它部件与其安装的基板的电路连接的麻烦，并且即使当非常高频率的噪声分量被输入到FET时，它们可以被吸收肯定不会增加其电路面积。解决方案：p型半导体衬底1的前表面侧具有作为二极管部分17的n型区域2b和作为晶体管部分16的n型阱区域2a。p型区域 9形成在二极管部分的n型区域2b中。包括p型区域的多个栅极区域3在阱区域2a中彼此平行地形成，每个栅极区域3的两侧的区域分别作为每个源极区域5和每个漏极区域4而工作。栅电极6，漏电极7和源电极8分别与这些各个区域3,4,5连接。反极性二极管17连接地设置在栅极和源电极6,8之间，电容器11是连接地设置在漏电源7和电源电极8之间。版权所有（C）2004，JPO＆NCIPI

3. 发明专利

JP2000200904A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000200904A
公开(公告)日：2000-07-18
申请号：JP123799
申请日：1999-01-06
申请人： ROHM CO LTD
发明人： HIGASHIDA YOSHIFUMI
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide an MOS FET for sufficiently reducing the trigger of a parasitic transistor, and for reducing the impurity concentration of a channel region. SOLUTION: N-type impurity is injected to one part of the surface of a high concentration (p)-type region 15 so that a low concentration (p) type region 19 can be formed in the part, and an (n)-type source region is formed in the high concentration (p) type region 15 so as to be made adjacent to the low concentration (p)-type region 19. Thus, the concentration of the impurity in the low concentration (p)-type region being a channel can be reduced, and the breakdown voltage of the parasitic transistor formed of an epitaxial layer 13, high concentration (p)-type region 15, and (n) type source region 19. That is, the threshold voltage of an MOS FET 1 can be decreased, and the L load resistant quantity and breakdown voltage or the like can be improved.

4. 发明专利

JP2014236171A 半導体装置およびその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014236171A
公开(公告)日：2014-12-15
申请号：JP2013118454
申请日：2013-06-05
申请人：ローム株式会社 , Rohm Co Ltd
发明人： HIGASHIDA YOSHIFUMI
IPC分类号： H01L29/47 , H01L21/329 , H01L29/872
CPC分类号： H01L29/872 , H01L21/26513 , H01L21/26586 , H01L29/0619 , H01L29/0634 , H01L29/0684 , H01L29/1608 , H01L29/417 , H01L29/66143 , H01L29/861
摘要：【課題】耐圧が向上し、リーク電流が抑制され、かつ低順方向電圧降下性能の半導体装置を提供する。【解決手段】半導体装置1は、第1導電型の半導体基板10と、半導体基板上にエピタキシャル成長により形成された第1導電型のドリフト領域14と、ドリフト領域に対して、所定のカラム幅L1およびドリフト領域幅L2を有し、多段イオン注入により複数形成された第1導電型のカラム領域30と、ドリフト領域の半導体基板とは反対側の表面上に配置され、ドリフト領域14とショットキー接触し、第1導電型のカラム領域30とオーミック接触するアノード電極20と、半導体基板のドリフト領域とは反対側の裏面上に配置され、半導体基板とオーミック接触するカソード電極24とを備える。【選択図】図1
摘要翻译：要解决的问题：提供具有改善的耐受电压，抑制泄漏电流和低正向压降性能的半导体器件。解决方案：半导体器件1包括：第一导电型半导体衬底10; 通过外延生长在半导体衬底上形成的第一导电型漂移区14; 具有相对于漂移区域具有预定列宽度的预定漂移区域宽度L的多个第一导电型列区域30，并通过多级离子注入形成; 布置在半导体衬底的相对侧上的漂移区的表面上的与漂移区14肖特基接触并与第一导电型列区30欧姆接触的阳极电极20; 以及阴极电极24，其设置在所述半导体衬底的与所述漂移区域相对的一侧的后表面上并与所述半导体衬底欧姆接触。

5. 发明专利

JP2013102111A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013102111A
公开(公告)日：2013-05-23
申请号：JP2012014415
申请日：2012-01-26
申请人： Rohm Co Ltd , ローム株式会社
发明人： NAKAJIMA TOSHIO , HIGASHIDA YOSHIFUMI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/739
CPC分类号： H01L29/0634 , H01L21/26513 , H01L29/0834 , H01L29/1095 , H01L29/7395 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a MOSFET which can reduce Rin a low-current range and perform conductivity modulation in a heavy-current range, and which can control device characteristics to device characteristics appropriate for application, and provide a manufacturing method.SOLUTION: A semiconductor device 1 comprises: an ntype base layer 2; a p type base layer 4 partially formed on a surface part of the ntype base layer 2; an nsource layer 5 partially formed on a surface part of the p type base layer 4; a gate insulation film 6 formed on a surface of the p type base layer 4 between the nsource layer 5 and the ntype base layer 2; a gate electrode 7 opposed to the p type base layer 4 across the gate insulation film 6; a p type column layer 3 formed in the ntype base layer 2 so as to continue to the p type base layer 4; a ptype collector layer 10 partially formed on a rear face part of the ntype base layer 2; a source electrode 8 electrically connected to the nsource layer 5; and a drain electrode 11 electrically connected to the nbase layer 2 and the ptype collector layer 10.
摘要翻译：要解决的问题：为了提供包括可以在低电流范围内降低上的R 解决方案：半导体器件1包括：基本层2; p型基底层4，其部分地形成在基底层2的表面部分上; 部分地形成在p型基底层4的表面部分上的n + 源层5; 形成在p型基底层4的表面上的栅极绝缘膜6在n + 源层5和n - >型基层2; 与栅极绝缘膜6相对的p型基极层4相对的栅电极7; 形成在p型基底层2中的p型列层3，以便继续到p型基底层4; 部分地形成在n - 型基层2的背面部分上的p + 型集电极层10; 与n + 源层5电连接的源电极8; 以及与n - / SP>基层2和p + 型集电极层10电连接的漏极11。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2010147176A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010147176A
公开(公告)日：2010-07-01
申请号：JP2008321295
申请日：2008-12-17
申请人： Rohm Co Ltd , ローム株式会社
发明人： HIGASHIDA YOSHIFUMI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0634 , H01L29/0649 , H01L29/1095 , H01L29/66712 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of which occurrence of a void in a drift region is suppressed.
SOLUTION: The semiconductor device includes a first conductive type semiconductor substrate 10 and a plurality of second conductive type semiconductor regions 21, 31-3n embedded respectively in a plurality of striped grooves formed in the semiconductor substrate 10 while being extended respectively in such row direction or column direction as parallel to a first main surface 101 of the semiconductor substrate 10 and being separated from each other at specific intervals. Depletion layers extending in the direction parallel to the first main surface 101 from a plurality of pn junctions formed respectively with the semiconductor substrate 10 and the semiconductor regions 21, 31-3n contact each other, so that the semiconductor substrate 10 and the semiconductor regions 21, 31-3n become depleted.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供抑制漂移区域中的空隙发生的半导体器件。解决方案：半导体器件包括分别嵌入形成在半导体衬底10中的多个条纹沟槽中的第一导电类型半导体衬底10和多个第二导电类型半导体区域21,31-3n，同时分别延伸行方向或列方向平行于半导体衬底10的第一主表面101并且以特定间隔彼此分离。从与半导体衬底10和半导体区域21,31-3n分别形成的多个pn结平行于第一主表面101的方向延伸的消耗层彼此接触，使得半导体衬底10和半导体区域21 ，31-3n变得枯竭了。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2000294770A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000294770A
公开(公告)日：2000-10-20
申请号：JP10327699
申请日：1999-04-09
申请人： ROHM CO LTD
发明人： HIGASHIDA YOSHIFUMI
IPC分类号： H01L29/06 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To obtain a MOSFET capable of improving its dielectric strength without destroying transistor cells even if surges in the reverse direction are applied instantly in association with inductive loads. SOLUTION: A plurality of p-type body regions 2 are formed in the surface of an n--type semiconductor layer 1 serving as a drain region, and source regions 3 are formed with n-type impurities introduced around each of the regions 2. Gate electrodes 6 are formed on the regions 3 through gate oxide films 5, whereby a plurality of transistor cells T are formed. A source electrode 12 is formed while connected to the regions 2 and 3 of the cells T. Further, at least two p-type diffusion regions 7 and 8 are formed in the surface of the layer 1 independently of the regions 2. The electrode 12 is connected also to the region 7, and the regions 7 and 8 are formed such that the distance (d) between them becomes wider than the distance (a) between the regions 2.

8. 发明专利

JP2008060149A Junction field effect transistor, and its manufacturing method 有权
标题翻译：连接场效应晶体管及其制造方法
公开(公告)号：JP2008060149A
公开(公告)日：2008-03-13
申请号：JP2006232328
申请日：2006-08-29
申请人： Rohm Co Ltd , ローム株式会社
发明人： HIGASHIDA YOSHIFUMI
IPC分类号： H01L21/337 , H01L29/808
CPC分类号： H01L29/808 , H01L29/42316 , H01L29/66893
摘要： PROBLEM TO BE SOLVED: To provide a junction field effect transistor wherein a channel area is formed uniform in thickness, and to provide its manufacturing method.
SOLUTION: In the junction field effect transistor 1; a p-type lower epitaxial layer 3, an n-type epitaxial layer 4, and a p-type upper epitaxial layer 5 are stacked on a semiconductor substrate 2 in this order from the side of the semiconductor substrate 2. A source area 7 and a drain area 9 are formed on a p-type upper epitaxial layer 5 while penetrating in its thickness direction, and they are connected with an n-type epitaxial layer 4. A gate electrode 11 is electrically connected with the p-type upper epitaxial layer 5 through the p-type lower epitaxial layer 3 and a p
+ -type area 6. Thus, the p-type upper epitaxial layer 5 becomes a gate area between the source area 7 and the drain area 9.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种结型场效应晶体管，其中沟道区域形成为均匀的厚度，并提供其制造方法。解决方案：在结场效应晶体管1中; p型下部外延层3，n型外延层4和p型上部外延层5从半导体基板2的侧面依次层叠在半导体基板2上。源极区域7和漏极区9在p型上部外延层5上沿其厚度方向穿透而形成，并与n型外延层4连接。栅电极11与p型上部外延层因此，p型上部外延层5成为源极区域7和漏极区域9之间的栅极区域。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2005123340A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005123340A
公开(公告)日：2005-05-12
申请号：JP2003355586
申请日：2003-10-15
申请人： Rohm Co Ltd , ローム株式会社
发明人： HIGASHIDA YOSHIFUMI , YATO SHINJI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with built-in resistor of a high resistance value for pull-up or pull-down into a semiconductor chip without raising the cost of the semiconductor chip.
SOLUTION: In the semiconductor device having a gate electrode pad 10 and a source electrode 20 on the surface of the semiconductor chip 2a, and provided with Zener diodes 21(21a, 21b, 21c) formed of polysilicon; high resistors 11(11a, 11b, 11c) formed of polysilicon are formed at the lower side of gate electrode pad 10 while both ends of them are electrically connected to the gate electrode pad 10 and the source electrode 20.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供具有高电阻值的内置电阻器的半导体器件，用于上拉或下拉到半导体芯片中，而不会增加半导体芯片的成本。解决方案：在半导体芯片2a的表面上具有栅电极焊盘10和源电极20的半导体器件中，并且设置有由多晶硅形成的齐纳二极管21（21a，21b，21c）在栅电极焊盘10的下侧形成由多晶硅形成的高电阻器11（11a，11b，11c），同时它们的两端与栅电极焊盘10和源电极20电连接。 C）2005，JPO＆NCIPI

10. 发明专利

JP2000294778A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000294778A
公开(公告)日：2000-10-20
申请号：JP10327499
申请日：1999-04-09
申请人： ROHM CO LTD
发明人： HIGASHIDA YOSHIFUMI , TAKAISHI AKIRA
IPC分类号： H01L29/78 , H01L27/04 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device having protection diodes whose breakdown voltage is high by providing diodes at two locations, utilizing a free area of a chip without increasing the area of the chip, and thereby increasing the number of diodes. SOLUTION: A first projection diode section 1 and a second protection diode section 2 are connected in series with each other by wires 3. The section 1 is formed by arranging annular n-type layers 1a and p-type layers 1b alternately around the periphery of a single electrode pad (gate electrode pad G). The section 2 is formed by arranging annular n-type layers 2a and p-type layers 2b made of a polysilicon film alternately around the periphery of the chip.

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