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    • 3. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPH11195732A
    • 1999-07-21
    • JP108298
    • 1998-01-06
    • MITSUBISHI ELECTRIC CORP
    • NOTANI YOSHIHIRO
    • H01L23/12H01L21/338H01L23/66H01L29/812H01P3/08H01P5/02H01P5/08
    • PROBLEM TO BE SOLVED: To prevent the increase in reflection loss, through impedance non- matching and to prevent parasitic oscillation. SOLUTION: A high frequency semiconductor chip 1 is provided with high frequency transmission lines L7a, and L7b of one surface and a ground conductor 5 of the other surface and a semiconductor package 8 is provided with the ground conductor 9 of one surface and the high frequency transmission lines L13a and L13b of the other surface. For this semiconductor device, the high frequency semiconductor chip 1 is loaded on the semiconductor package 8 and slots 4a, 10a, 4b and 10b are formed at the ground conductors 5 and 9 so as to respectively face each other and to face the high frequency transmission lines L7a, L13a, L7b and L13b and are electromagnetically connected between the high frequency transmission lines L7a and L13a and between the high frequency transmission lines L7b and L13b. Also, Ni conductors are formed on the ground conductor 5 which is positioned at the peripheral part of the slots 4a and 4b or the Ni conductors are formed on the ground conductor 9 positioned at the peripheral part of the slots 10a and 10b.
    • 7. 发明专利
    • MANUFACTURE OF FIELD EFFECT TRANSISTOR
    • JPH02122632A
    • 1990-05-10
    • JP27798288
    • 1988-11-01
    • MITSUBISHI ELECTRIC CORP
    • NOTANI YOSHIHIRO
    • H01L29/812H01L21/285H01L21/338H01L29/41
    • PURPOSE:To improve resistant pressure of a gate of a multilayer structure of FET by a method wherein evaporation of gate metal at the lowest layer in a multilayer gate is carried out from a slant direction. CONSTITUTION:After an n-type GaAs operation layer 2, a drain electrode 3, a source electrode 4 and a recess 5 are formed on a semi-insulating GaAs substrate 1, a resist 12 for forming a gate is applied, and gate metal A6 is deposited perpendicularly. Then, the gate metal A6 is evaporated in an evaporation direction D14 on only the resist 12 with an evaporation angle theta16 (approximately 45 deg. or smaller). Then, by evaporating the gate metal A6 from an evaporation direction E15 with the evaporation angle theta16 (approximately 45 deg. or smaller) only on the resist, the original resist 12 becomes a little larger due to the gate metal 6, to have opening width d17 reduced. Then, remaining gate metals B7 to D9 are deposited perpendicularly. This permits gate metals other than the gate metal A6 due to transfer of the resist or the like to be in contact with the n-type GaAs operating layer 2 preventing deterioration in gate resistant pressure and FET performance.