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1. 发明专利

JPS57111733A BUS CONVERSION SYSTEM 失效
公开(公告)号：JPS57111733A
公开(公告)日：1982-07-12
申请号：JP18540780
申请日：1980-12-29
申请人： PANA FACOM KK
发明人： YAMAGUCHI TAHEI , HAIDA HIROTOSHI , MASUDA TOMIO , SATOU NOBUAKI , OKUNO ITARU
IPC分类号： G06F13/36 , G06F5/00 , G06F13/40
摘要： PURPOSE:To raise the throughput of a CPU, by providing a low-speed bus for transferring data of unit quantity, a high-speed bus for transferring data of (n) unit qantity, and a corresponding address information storing buffer, and converting the data between both the buses by a control means. CONSTITUTION:This system is provided with a low-speed bus 1 for transferring data of unit quantity, a high-speed bus 2 for transferring data of (n) unit quantity, and a buffer 3 for storing the data of (n) unit and an address information corresponding to said data, and the data between both the buses is converted by a control means 4. In case when data is transferred to the bus 2 side from the bus 1 side, the means 4 writes the data in order in the buffer 3, and when it is written, a timer is reset, and after that, the timer is restarted, and when the buffer becomes full and the timer becomes time-over, said means controls so that the data is sent out to the bus 2. In case when data is transferred to the bus 1 from the bus 2, the means sends out the data to the bus if request data is in the buffer, requests it to the CPU and inputs it to the buffer if not any, and after that, sends it out to the bus 1, and controls so that the buffer is released in case of time-over.

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