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1. 发明专利

JP2009272987A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009272987A
公开(公告)日：2009-11-19
申请号：JP2008123148
申请日：2008-05-09
申请人： Oki Micro Design Co Ltd , Oki Semiconductor Co Ltd , Okiセミコンダクタ株式会社 , 株式会社沖マイクロデザイン
发明人： FUJIEDA WAICHIRO
IPC分类号： H03K5/14
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that generates a signal whose delay amount is different without increasing not only a layout area but also a constantly flowing current. SOLUTION: A pulse generating portion including a plurality of delay circuit portions (4a, 4b) for changing a delay time in response to the applied voltage and a reference voltage generating circuit portion 2 for generating different types of voltages responsive to each pulse signal output by the pulse generating portion are disposed in the semiconductor device. This results in generating different types of delay amount signals by applying the voltage generated by the reference voltage generating circuit portion 2 to the delay circuit portions (4a, 4b) of the pulse generating portion. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其产生延迟量不同而不增加布局面积而且不增加恒定流动电流的信号。解决方案：一种脉冲发生部分，包括用于响应于施加的电压改变延迟时间的多个延迟电路部分（4a，4b）和用于响应于每个脉冲产生不同类型的电压的参考电压产生电路部分2 脉冲发生部分的信号输出设置在半导体器件中。这导致通过将由基准电压发生电路部分2产生的电压施加到脉冲发生部分的延迟电路部分（4a，4b）来产生不同类型的延迟量信号。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2011090734A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2011090734A
公开(公告)日：2011-05-06
申请号：JP2009242615
申请日：2009-10-21
申请人： Oki Semiconductor Co Ltd , Okiセミコンダクタ株式会社
发明人： FUJIEDA WAICHIRO
IPC分类号： G11C16/06 , G11C17/12
CPC分类号： G11C7/12 , G11C17/123
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a leak current flowing into a bit line from a signal line for outputting a taken-out signal to the outside can be suppressed. SOLUTION: Specifically, an NMOS transistor 38 is connected to an NMOS transistor 34 in series, the source of a PMOS transistor 40 is connected to a power source, and a drain is connected to a node N between the NMOS transistor 34 and the NMOS transistor 38. Accordingly, when a data line signal "data" is pre-charged to an [H] level, in a bit line selecting circuit 23 to which a bit line selecting signal V of an [L] level being a non-selection signal is input, the node N is pre-charged to the [H] level, and since a potential difference between the source and the drain of the NMOS transistor 34 is no longer present, a leak current flowing into the bit line BL from the data line "data" through the node N is prevented. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体存储器件，其中可以抑制从用于输出取出信号的信号线流入位线的漏电流到外部。解决方案：具体地，NMOS晶体管38串联连接到NMOS晶体管34，PMOS晶体管40的源极连接到电源，漏极连接到NMOS晶体管34和NMOS晶体管34之间的节点N. 因此，当数据线信号“数据”被预充电为[H]电平时，在位线选择电路23中，[L]电平的位线选择信号V为非“ - 选择信号，节点N被预充电到[H]电平，并且由于不再存在NMOS晶体管34的源极和漏极之间的电位差，所以流入位线BL的漏电流从数据线“数据”通过节点N被阻止。版权所有（C）2011，JPO＆INPIT

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