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1. 发明专利

JPH01173138A PARITY ADDING/CHECKING SYSTEM 失效
公开(公告)号：JPH01173138A
公开(公告)日：1989-07-07
申请号：JP33012387
申请日：1987-12-28
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HACHITSUKA SHOZO , AKIYAMA NOBUYOSHI
IPC分类号： G06F11/10 , G06F12/16
摘要： PURPOSE:To obtain a compact and light-weight device for parity addition/check by controlling the write timing of a 2nd memory and the parity check timing of a checking means based on some bits of an input address given to a 1st memory and supplying the input address excluding some bits to the 2nd memory. CONSTITUTION:In a write state of a parity memory 9, a control part (a gate, etc.) 16 controls the write timing based on some bits of an input address so that the parity bits supplied from a parity generating means 8 for each input data of the prescribed number of bit units (byte unit, etc.) are thinned and stored in a voice memory 6. In the read states of both memories 9 and 6, the means 16 functions to control the parity check timing for a checking means 10 based on some bits of the input address. When some bits of the input address are equal to the lower three bits, for example, one parity bit is added every 8 bytes and the parity check is performed every 8 bytes. In such a way, a compact and light-weight device is obtained for parity addition/check.

2. 发明专利

JPS5122301A 失效
公开(公告)号：JPS5122301A
公开(公告)日：1976-02-23
申请号：JP9462774
申请日：1974-08-20
申请人： OKI ELECTRIC IND CO LTD
发明人： MATSUNO TETSUYA , HACHITSUKA SHOZO
IPC分类号： H04M3/42 , H04M1/00 , H04M1/02 , H04M1/26 , H04Q3/58

3. 发明专利

JPS5120614A 失效
公开(公告)号：JPS5120614A
公开(公告)日：1976-02-19
申请号：JP9197674
申请日：1974-08-13
申请人： OKI ELECTRIC IND CO LTD
发明人： FUNAKI KINYA , HACHITSUKA SHOZO
IPC分类号： H04M3/42 , H04M3/60 , H04Q3/42 , H04Q3/58

4. 发明专利

JPS62171299A REMOTE CONTROL EXCHANGE SYSTEM 失效
公开(公告)号：JPS62171299A
公开(公告)日：1987-07-28
申请号：JP1107486
申请日：1986-01-23
申请人： OKI ELECTRIC IND CO LTD
发明人： OKAYASU MASAHARU , SAITO JINKO , HACHITSUKA SHOZO
IPC分类号： H04Q11/04 , H04Q3/60
摘要： PURPOSE:To simplify the communication software and to reduce the transmission time by assigning the 1st SAPI identifier to control communication between a remote station and a master station and the 2nd SAPI identifier to communication between processors, using a UI frame to control communication and applying multi-frame transfer to communication between processors. CONSTITUTION:A master station has a function controlling forcibly a remote station and the remote station has a function to inform its state to the master station. Thus, a signal processing unit 10A of the remote station and a signal processing unit 10B of the master station are connected by one line 108. A role shown in figure is assigned to specific identifiers '15', '31' among idle identifiers in a conventional system. That is, in controlling the peripheral of the processor of the remote station directly, the identifier SAPI is set to '31', a system controller 30 uses the UI frame and processes it, and the identifier SAPI is set to '15' for the communication between processors of both the stations and in the remote station, a remote control processor 40 the same as the handing of the conventional subscriber line signal processes the data by multi-frame transfer of LapD. Further, the master station uses the control processor 8 to process the both cases.

5. 发明专利

JPS6149262A Page memory information transfer system 失效
标题翻译：页面存储信息传送系统
公开(公告)号：JPS6149262A
公开(公告)日：1986-03-11
申请号：JP16995384
申请日：1984-08-16
申请人： Oki Electric Ind Co Ltd
发明人： KISHINO NORIAKI , ABE MINORU , FURUHASHI TORU , NAKAMURA HITOYA , HACHITSUKA SHOZO
IPC分类号： G06F13/38 , G06F12/00 , G06F15/17
CPC分类号： G06F15/17
摘要： PURPOSE:To transfer a large quantity of information with high speed by accumulating information to be transferred at a memory and controlling so as to operate under a device which should receive the memory. CONSTITUTION:Processing devices 1a and 1b have transfer buses 2a and 2b respectively, ''empty'' of a page memory 3 is informed by an empty information 4a from the processing device 1b to the processing device 1a, it is informed by a transfer request 5a that a request of information transfer occurs from the processing device 1a to the processing device 1b. ''Empty'' of the page memory 3 is informed by an empty information 4b from the processing device 1a to the processing device 1b and it is informed by a transfer request 5b that information is transferred from the processing device 1b to the processing device 1a. A page memory control part 6 controls that by an order from the processing device 1b the page memory 3 is connected to the transfer bus 2a or it is connected to the transfer bus 2b.
摘要翻译：目的：通过积累要在存储器中传送的信息并进行控制以便在应该接收存储器的设备下运行，高速传输大量信息。构成：处理装置1a和1b分别具有传送总线2a和2b，页存储器3的“空”由空信息4a从处理装置1b通知给处理装置1a，通过传送请求如图5a所示，从处理装置1a到处理装置1b发生信息转移请求。通过从处理装置1a向处理装置1b的空信息4b通知页存储器3的“空”，并且由传送请求5b通知信息从处理装置1b传送到处理装置1a 。页面存储器控制部分6通过来自处理装置1b的命令来控制页面存储器3连接到传送总线2a或者它连接到传送总线2b。

6. 发明专利

JPS6148256A Processor of isdn subscriber line signal 失效
标题翻译： ISDN订户信令的处理器
公开(公告)号：JPS6148256A
公开(公告)日：1986-03-08
申请号：JP16995284
申请日：1984-08-16
申请人： Oki Electric Ind Co Ltd
发明人： FURUHASHI TORU , ABE MINORU , KISHINO NORIAKI , NAKAMURA HITOYA , HACHITSUKA SHOZO
IPC分类号： H04Q3/545 , H04L12/64 , H04M3/00 , H04Q11/04
摘要： PURPOSE: To miniaturize a processor and to apply it to a terminal device in common to different kinds of devices by adopting a multiplexed hierarchy for the processing section.
CONSTITUTION: A signal processor 1 is subject to hierarchy structure in its inside into signal processing sections 2 and 3, which share subscriber signal device procedures. The signal processing 2 applies m-multiplex to a D channel at each subscriber via a multiplexer 7 and becomes a logical termination to each channel. Since the signal processing section 2 is of n-multiple constitution in the entire processor, (m)×(n)-set of D channels are processed multiplexingly.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过采用处理部分的多路复用层级，使处理器小型化并将其应用于不同种类设备的终端设备。构成：信号处理器1在其内部受到层级结构的信号处理部分2和3，其共享用户信号装置过程。信号处理2经由多路复用器7在每个用户处将M复用应用于D信道，并且成为每个信道的逻辑终止。由于信号处理部分2在整个处理器中是n倍的结构，所以（m）X（n）个D信道的集合被多路复用处理。

7. 发明专利

JPS5121716A 失效
公开(公告)号：JPS5121716A
公开(公告)日：1976-02-21
申请号：JP9382174
申请日：1974-08-17
申请人： OKI ELECTRIC IND CO LTD
发明人： OKANO HIROTAKA , HACHITSUKA SHOZO
IPC分类号： H04M3/60

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