专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2000249744A ELECTRONIC CIRCUIT DEVICE AND TEST METHOD THEREOF 失效
公开(公告)号：JP2000249744A
公开(公告)日：2000-09-14
申请号：JP5097599
申请日：1999-02-26
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： EJIMA YOSHIYUKI , NAKAMURA HITOYA , YAMANAKA NAOAKI , KAWAMURA TOMOAKI
IPC分类号： H05K13/08 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide an electronic circuit device lowering production costs and a test method thereof. SOLUTION: A test-only wiring pattern 5 is arranged on a base board 1 for every tested pair chip 6 so as to be connected to a testing terminal 10. In test of the device, first of all, only a single tested pair chip 6 is mounted for testing whether it is good or defective. When it is confirmed to be good, the following tested pair chip 6 is also mounted so as to be tested. When the last tested pair chip 6 is mounted, a function test as an electronic circuit device is carried out, and when it is determined to be good, the electronic circuit device is completed.

2. 发明专利

JPH03295339A TEST SYSTEM FOR PROTOCOL VERIFICATION 失效
公开(公告)号：JPH03295339A
公开(公告)日：1991-12-26
申请号：JP9619190
申请日：1990-04-13
申请人： OKI ELECTRIC IND CO LTD
发明人： INAGAKI TOSHIHIKO , KISHINO NORIAKI , NAKAMURA HITOYA , WATANABE NOBORU
IPC分类号： H04L29/06 , H04L29/14
摘要： PURPOSE:To attain the perfectly automated execution of a test and the improvement of the certainty of verification by selecting automatically and at random the procedure of transition from an initial state to the state of a testing condition from among test tasks existing in plural kinds by using a random number at every execution of the test. CONSTITUTION:By using the function of a testing procedure generating part 11 provided with a pre-procedure generating function to generate automatically and at random the procedure of the transition from the initial state to the present state of the test for verification and an after-procedure generating function to generate automatically and at random the procedure of the transition from the present state of the test for verification to the initial state, the test is always executed by different procedures at every execution of the same test even in the state of the same testing condition. Besides, a random number generator 13 is used for generating the procedure of the transition at random. Thus, in the case the same test is executed plural number of times, the procedure of the transition from the initial state to the state of the test condition is changed at every execution of the test, and the certainty of the verification is raised, and in addition, the perfect automation of protocol verification is attained.

3. 发明专利

JPH0378660B2 失效
公开(公告)号：JPH0378660B2
公开(公告)日：1991-12-16
申请号：JP28724385
申请日：1985-12-20
申请人： OKI ELECTRIC IND CO LTD
发明人： KISHINO NORIAKI , FURUHASHI TOORU , NAKAMURA HITOYA , ABE MINORU
IPC分类号： H04L29/10 , G06F3/06 , G06F12/02 , G06F12/04 , G06F13/00 , G06F13/38 , H04L13/00 , H04L13/08

4. 发明专利

JPH0230254A MULTIPLEX TRANSMITTER-RECEIVER IN HIGH LEVEL DATA LINK CONTROL PROCEDURE 失效
公开(公告)号：JPH0230254A
公开(公告)日：1990-01-31
申请号：JP17909088
申请日：1988-07-20
申请人： OKI ELECTRIC IND CO LTD
发明人： KISHINO NORIAKI , NAKAMURA HITOYA , FURUHASHI TORU
IPC分类号： H04L5/22 , H04L13/00 , H04L29/08
摘要： PURPOSE:To attain high speed transmission by executing the processing in the unit of one bit in the processing timing synchronously with the 1-bit unit for each channel. CONSTITUTION:Upon the receipt of an 8-bit serial data from a reception signal line RXD, a demultiplexer DEMUX branches the data to channels CHO, CHI and the data is sent to reception circuits RSP0, RSP1 respectively. The reception circuits RSP0, RSP1 convert the incoming data into an 8-bit parallel (1 word) data while applying flag detection and abort error check in the unit of one bit and send the result to a reception processing circuit RPR. The processing circuit RPR according to a timing circuit TIM reads out status information from a save memory RLM in the processing for each channel (processing in the unit of words) to make the preceding processing consecutive.

5. 发明专利

JPS61193539A DIGITAL LINE TEST SYSTEM 失效
公开(公告)号：JPS61193539A
公开(公告)日：1986-08-28
申请号：JP3288685
申请日：1985-02-22
申请人： OKI ELECTRIC IND CO LTD
发明人： FURUHASHI TORU , YAMADA HAJIME , NAKAMURA HITOYA
IPC分类号： H04L5/22 , H04L13/00 , H04L29/14
摘要： PURPOSE:To attain execution of a test of an information line with a part of device only by allowing the transmission side to define the test mode to a control field at test, sending a frame given with a test pattern and allowing the reception side to reflect the test pattern of an information field to the transmission side. CONSTITUTION:A remote test device 5 sends data to a DTE 1-1 by the loop 2 mode designation, then a DSU 3 gives information directly to the DTE as it is in the same way as other normal frame. The DTE 1-1 uses a field A to recognize the information to the DTE 1-1 and uses a field C to recognize the loop 2 mode. The DTE 1-1 returns the test pattern represented by one field as it is. In this case, as the return system by the DTE, it is considered that two ways such as the realizing system returning four fields A, C, I, FCS like the DSU 3 and the system processing fields A, C and any of the systems is used by deciding the system in advance between the DTE and the remote test device 5. Thus, the test is conducted without giving effects on a logical channel having no fault at the time of fault occurrence.

6. 发明专利

JPH06338922A SYSTEM SWITCHING SYSTEM 失效
公开(公告)号：JPH06338922A
公开(公告)日：1994-12-06
申请号：JP12742593
申请日：1993-05-28
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAMURA HITOYA , SUDA HIDEKAZU
IPC分类号： H04B1/74 , H04L1/22 , H04L29/10 , H04L29/14
摘要： PURPOSE:To prevent the influence on an opposed equipment by reducing a processing time at the time of system switching of layer 2 equipments. CONSTITUTION:This system is on the premise of a signal processor provided with the layer 2 equipments 53 and 54 provided with redundant constitution which provides plural data link connections. When a data link connection identification data value is assigned to a layer 2 equipment of an operation system, the same data link connection identification data value is assigned to a layer 2 equipment of a preparatory system. On the other hand, when the data link connection identification data value is assign-released to the layer 2 equipment of the operation system, the same data link connection identification data value is assign-released to the layer 2 equipment of the preparatory system. Thus, the layer 2 equipment of the preparatory system is made to be in the state of always being assigned with the data link connection identification data value so as to execute a start processing from the assigned state of the data link connection identification data value at the time of system switching.

7. 发明专利

JPH05336156A 失效
公开(公告)号：JPH05336156A
公开(公告)日：1993-12-17
申请号：JP14262992
申请日：1992-06-03
申请人： OKI ELECTRIC IND CO LTD
发明人： ASO JIRO , NAKAMURA HITOYA , NIITAKA KOJI , KISHINO NORIAKI
IPC分类号： H04J3/00 , H04Q11/04 , H04L12/48
摘要： PURPOSE:To eliminate a limit of an accommodated path number due to a mem ory capacity required for managing the composition state of a frame. CONSTITUTION:A frame identification number allocation section 27 allocates a frame identification number to a frame at the start of composition of each frame. Thus, the composition state of each frame is managed by a frame composition state control section 30 based on the frame identification number. When the composition of each frame is finished, the frame identification number allocated by the frame is released from a frame identification number allocation section 27.

8. 发明专利

JPH03201634A MAINTENANCE INFORMATION TRANSFER SYSTEM 失效
公开(公告)号：JPH03201634A
公开(公告)日：1991-09-03
申请号：JP33832889
申请日：1989-12-28
申请人： OKI ELECTRIC IND CO LTD
发明人： NAKAMURA HITOYA , KISHINO NORIAKI , YAMAMOTO TAKASHI
IPC分类号： H04B17/00 , H04B17/18 , H04B17/29
摘要： PURPOSE:To read maintenance information from a host device at anytime and to easily collect the maintenance information at real time whenever the host device requires the information by providing a maintenance information memory, memory clearing means and maintenance information updating means. CONSTITUTION:When an event to update the maintenance information is generated at an information transmitter-receiver 30, maintenance information updating means 32 and 37 are activated to update the maintenance information, which are stored in a maintenance information memory 30, concerning the generated event. In such a manner, the contents of the maintenance information memory 330 are always updated to the latest state. Since the maintenance information memory 330 is not set in the direct control of a central processing unit 32 at the information transmitter-receiver 30, the host device 40 can execute read access to the area of the maintenance information memory, where the required maintenance information are stored, at an arbitrary time point. Thus, the maintenance information can be collected at real time whenever the host device 40 requires the information. Further, the ability of a slave device 30 to be consumed for a monitoring operation processing can be reduced.

9. 发明专利

JPH0389754A EXECUTION MANAGEMENT PROCESSING SYSTEM IN COMMUNICATION CONTROL PROCESSING EQUIPMENT 失效
公开(公告)号：JPH0389754A
公开(公告)日：1991-04-15
申请号：JP22452189
申请日：1989-09-01
申请人： OKI ELECTRIC IND CO LTD
发明人： NAKAMURA HITOYA , KISHINO NORIAKI , INAGAKI TOSHIHIKO , YAMAMOTO TAKASHI
IPC分类号： G06F13/00 , H04L29/02 , H04L29/08
摘要： PURPOSE:To suppress wasteful processing to minimum, and to shorten the processing time by adjusting the number of events stagnating in a main queue less than a fixed number by using an event input selecting function and an event circulating function. CONSTITUTION:The number of the events stagnating in the main queue 12 is adjusted to be less than the fixed number at every data link based on the pieces of information stagnating in sub-queues 12A to 12N prepared at every data link by the event input selecting function 61 and the event circulating function 62, and the number of the events stagnating in the main queue 12 is suppressed to necessary minimum at every data link. Thus, the occurrence of such a situation that the many events for which the data link stagnates in the main queue 12 and transmission becomes impossible can be prevented, and the wasteful processing at the time when frame transmission is impossible can be suppressed to the minimum, and the processing time can be shortened, and simultaneously, processing efficiency can be improved.

10. 发明专利

JPH0368877A LSI TESTING CIRCUIT 失效
公开(公告)号：JPH0368877A
公开(公告)日：1991-03-25
申请号：JP20451889
申请日：1989-08-07
申请人： OKI ELECTRIC IND CO LTD
发明人： NAKAMURA HITOYA , KISHINO NORIAKI , NIITAKA KOJI , YAMAMOTO TAKASHI
IPC分类号： G01R31/28 , H01L21/66
摘要： PURPOSE:To reduce a test executing period and a test data preparing time by inputting divided test data to a sequencer circuit and a combination circuit through a data bus and taking out the data to collate the same with an expected value. CONSTITUTION:Test data are inputted to a combination circuit 10 from input terminals IN1 - INn. Next, test mode control signals C1 - Cn are inputted to a selector 14-1 by a gate signal (r) to output a test starting signal S2. Next, the test data are inputted from test input/output terminals T1 - Tn and one test clock signal TCK 1 is inputted to latch the test data by F/F 11b-1 - 11b-n. Try state buffers 13b-1 - 13b-n are started by a test starting signal S3 and the output data of a combination circuit 11 are outputted to the test input/output terminals T1 - Tn. Then, the output values thereof are collated with an expected value. By this method, the number of test cycles are reduced and a data preparing time can be reduced to a large extent.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式