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1. 发明专利

JPH1056466A TRAFFIC LEVELING DEVICE IN ATM EXCHANGE SYSTEM 失效
公开(公告)号：JPH1056466A
公开(公告)日：1998-02-24
申请号：JP22459296
申请日：1996-08-08
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MIZUNO HIROYASU , TAKEUCHI TAKEHISA , ENDO YASUSHI , USHIJIMA SHIGEHIKO , NORITAKE KATSUSHI
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide the traffic leveling device in which the service is uniformly provided even when any virtual path is in use independently of a set band and no cell abort is caused. SOLUTION: The device 10 levels an operating band of cells transferred in an asynchronous transfer made(ATM) network over a plurality of kinds of virtual paths VP and virtual channels VC (logic channels) and transfers the leveled cells. Upon the receipt of cells 102 statistically multiplexed, the cells are stored tentatively in a cell memory 20 and the number of the stored input cells 102 is counted by an in-buffer cell number counter 28 corresponding to the logic channel. An output timing generating section 12 calculates an output enable time 126 corresponding to the operating band of the cells 102 corresponding to the logic channel in response to the increase/decrease in the count. Depending on the output enable time 126, the cells 102 are read from the cell memory 20 and sent. Thus, the cells 102 are sent at a uniform band in matching the traffic characteristic allowed by the opposite party equipment to be sent as to any logic channel.

2. 发明专利

JPH1056465A MULTIPLE ADDRESS FIXED LENGTH CELL DISASSEMBLING DEVICE 失效
公开(公告)号：JPH1056465A
公开(公告)日：1998-02-24
申请号：JP22459196
申请日：1996-08-08
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OKUNO MIKIFUMI , MIZUNO HIROYASU , SENDA KOICHI , USHIJIMA SHIGEHIKO , NORITAKE KATSUSHI
IPC分类号： H04Q3/00 , H04L12/24 , H04L12/26 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a multiple address fixed length cell disassembler in which a copy multiple address asynchronous transfer mode(ATM) cell is not returned to a caller terminal equipment contained in its own node through multiple address communication by means of a simple circuit. SOLUTION: In the case that a multiple address containing multiple address to which caller terminal equipments contained in the same own node belong from both a path information filter 60 and a subscriber system path registration memory 80, a virtual path identification address containing an address '00' to identify its own node, and a virtual channel identification address containing an address '16' to identify a caller terminal equipment contained in its own node are sent to a path information comparator 86, the path information comparator 86 outputs an abort control signal to a transmission data control circuit 70 to abort a copied multiple address ATM cell to the caller terminal equipment contained in its own node. Thus, the copy multiple address ATM cell is not returned to the caller terminal equipment contained in its own node with a simple circuit system.

3. 发明专利

JPH09284327A DELAY SHORTENING METHOD FOR LAN EQUIPMENT 失效
公开(公告)号：JPH09284327A
公开(公告)日：1997-10-31
申请号：JP8612596
申请日：1996-04-09
申请人： OKI ELECTRIC IND CO LTD
发明人： MIZUNO HIROYASU , KOBAYASHI SHOJI , OKUNO MIKIFUMI , ARAKAWA NOBUYA
IPC分类号： H04L12/28 , H04L12/46 , H04L12/66 , H04L12/70 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a delay shortening method for shortening the delay time of a packet in a LAN equipment. SOLUTION: A packet receiving part 11 stores a packet received from LAN 1 in a reception packet buffer 12. When information required for a routing processing is stored in the reception packet buffer 12, a routing processing part 3 reads the information without waiting a packet reception end, starts the routing processing and generates an applying MAC(media access control) header. The reception packet buffer 12 adds the MAC header to the received packet and generates a transmission packet. The transmission packet is transferred from the reception packet buffet 12 to a transmission packet buffer 21. A packet transmitting part 22 reads the transmission packet from the transmission packet buffer 21 at prescribed speed and transmits it to LAN 2.

4. 发明专利

JPH08251189A ATM COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH08251189A
公开(公告)日：1996-09-27
申请号：JP5296095
申请日：1995-03-13
申请人： OKI ELECTRIC IND CO LTD
发明人： KONDO TOSHIHIRO , MIZUNO HIROYASU , TANAKA TAKESHI , ASO JIRO
IPC分类号： H04Q3/00 , H04L12/28
摘要： PURPOSE: To realize a ATM(asynchronous transfer mode) communication equipment not provided with a shaping function in the case where this function is not required. CONSTITUTION: An ATM line terminal part 11 and an SHP(shaper part) 12 are connected to each other by connectors 14, 15. A LAN line terminal part 13 and the SHP 12 are connected to each other by the connectors 16, 17. The physical interface of the ATM line terminal part 11 at the connection point A of the ATM line terminal part 11 and the SHP 12 and the physical interface of the LAN line terminal part 13 at the connection point B of the LAN line terminal part 13 and the SHP 12 are set so as to be equal.

5. 发明专利

JPH05199223A CHARGING SYSTEM FOR ATM EXCHANGE NETWORK 失效
公开(公告)号：JPH05199223A
公开(公告)日：1993-08-06
申请号：JP889992
申请日：1992-01-22
申请人： OKI ELECTRIC IND CO LTD
发明人： FUJII SHIGERU , KOBAYASHI SHOJI , MIZUNO HIROYASU
IPC分类号： H04L12/14
摘要： PURPOSE:To enable charging just for valid data received at an ATM exchange network. CONSTITUTION:Since an ATM node on the reception side are valid data from a cell 1 to a cell n-1 and a cell (n) is invalid data having CRC error, etc., charging is executed to (n-1) data from the cell 1 to the cell n-1 as the valid data, and charging is not executed to the cell (n) as the invalid data after the CRC error or the like is detected. Even when any cell is missed, this is detected, and charging is not executed similarly.

6. 发明专利

JPH10112728A ASSOCIATIVE MEMORY RETRIEVAL SYSTEM 失效
公开(公告)号：JPH10112728A
公开(公告)日：1998-04-28
申请号：JP26451196
申请日：1996-10-04
申请人： OKI ELECTRIC IND CO LTD
发明人： MIZUNO HIROYASU
IPC分类号： G11C15/04 , G06F17/30 , H04L12/66 , H04L12/701 , H04L12/741 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To increase an operating speed of destination address retrieval of transfer data with a router of a LAN. SOLUTION: Each retrieval circuit consists of 32-bit registers. An address '12345600H' is registered as an address NA + SNA of a subnetwork in a registration data register 41, a subnet mask 'FFFFFF00H' is made initial setting and N addresses NA + SNA and their subnet masks are set in a mask register 51. An IP address '12345600H' of a retrieval data register 33 is inputted to comparators 61 to 6N, and the address of a registration data register 41 and the subnet mask of a mask register 51 are inputted to a comparator 61. The comparator 61 compares the value which masks the IP address through a subnet mask with an address from the register 41 and outputs 'coincidence' from an output 35. Because addresses of subnet masks are entirely different within the same LAN, comparators 62 to 6N of other registration data registers 42 to 4N outputs 'uncoincidence' from the output 35.

7. 发明专利

JPH05219112A PACKET HEADER ADDING SYSTEM 失效
公开(公告)号：JPH05219112A
公开(公告)日：1993-08-27
申请号：JP1809092
申请日：1992-02-04
申请人： OKI ELECTRIC IND CO LTD
发明人： KOBAYASHI SHOJI , FUJII SHIGERU , MIZUNO HIROYASU
IPC分类号： H04L12/70
摘要： PURPOSE:To add a packet header different for every packet information data without imposing load upon a microprocessor. CONSTITUTION:Input data consisting of the packet information data (b) and a packet header information address (c) is inputted to a packet information data buffer 1. A packet header information memory read-out control part 5 accesses a packet header information memory 4 by using the packet header information address (c) read out of the packet information data buffer 1, and reads out packet header information (a), and sends it to a packet header adding part 3. Next, a timing control part 6 controls a system so as to read the packet information data (b) out of the packet information data buffer 1, and fetch it as the input of the packet header adding part 3. The packet header adding part 3 outputs packet data which is the packet information data (b) added with the packet header information (a).

8. 发明专利

JPH052553A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPH052553A
公开(公告)日：1993-01-08
申请号：JP18022191
申请日：1991-06-25
申请人： OKI ELECTRIC IND CO LTD
发明人： MIZUNO HIROYASU
IPC分类号： G06F13/28
摘要： PURPOSE:To save a communication time and to attain quick access by forming a succeeding address signal based upon a current address signal for memory access and executing the memory access prior to the formation of the succeeding address signal. CONSTITUTION:A circuit for selecting prescribed address generation order based upon an identification(ID) signal 10-2 is included in a memory controller 20. The controller 20 receives the ID signal for specifying the address generation order from the processor 10, independently forms a new succeeding address signal based upon a current address signal for memory access which is inputted from the processor 10 and executes the memory access prior to the formation of the succeeding address signal. As compared with the case for forming all address signals by the processor 10 and executing memory access based upon the formed address signals, a communication time between the processor 10 and the memory controller 20 can be saved and quick access can be attained.

9. 发明专利

JPH1056467A TRAFFIC SHAPING DEVICE 失效
公开(公告)号：JPH1056467A
公开(公告)日：1998-02-24
申请号：JP22600696
申请日：1996-08-08
申请人： OKI ELECTRIC IND CO LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEUCHI TAKEHISA , ENDO YASUSHI , MIZUNO HIROYASU , USHIJIMA SHIGEHIKO , NORITAKE KATSUSHI
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/70 , H04L12/815 , H04L12/863
摘要： PROBLEM TO BE SOLVED: To facilitate timing control of a read/write cycle to a common cell buffer. SOLUTION: A buffer management section 4 discriminates whether or not an output cell 102 is in existence when an input cell 101 to a common cell buffer 1 is given. When the output cell 102 is in existence, a read address from the common cell buffer 1 is latched by a register 2. A memory access control section 11 uses a write address of the input cell 101 to be an address latched by a register 102 when the buffer management section 4 discriminates the presence of the output cell 102.

10. 发明专利

JPH05199225A SYSTEM FOR COMMUNICATION BETWEEN LAN 失效
公开(公告)号：JPH05199225A
公开(公告)日：1993-08-06
申请号：JP890092
申请日：1992-01-22
申请人： OKI ELECTRIC IND CO LTD
发明人： MIZUNO HIROYASU , FUJII SHIGERU , ENDO YASUSHI
IPC分类号： H04L12/46 , H04L12/28
摘要： PURPOSE:To enable communication between LANs having MAC addresses with the different number of bits. CONSTITUTION:Data received from a LAN 11 of 16 bits are transmitted through a transmission/reception port part 1a to an address translation part 3. The address translation part 3 retrieves an address correspondence table 4 concerning the destination MAC address of 16 bits in the received data and obtains the destination MAC address of 48 bits. Further, the transmission source MAC address of 48 bits is obtained concerning the transmission source MAC address of 16 bits in the received data. The MAC address of 48 bits obtained like this is exchanged with the MAC address of 16 bits in the received data and transmitted through a transmission/reception port part 1b to a LAN 12 of 48 bits by executing an original inter-LAN connection processing at an original function part 2. Data received from the LAN 12 of 48 bits are similarly processed as well.

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