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1. 发明专利

JPH09205437A COMPETING PACKET MEDIATION DEVICE FOR SELECTIVE BROADCAST AND PACKET EXCHANGE SYSTEM 失效
公开(公告)号：JPH09205437A
公开(公告)日：1997-08-05
申请号：JP1176996
申请日：1996-01-26
申请人： OKI ELECTRIC IND CO LTD
发明人： KITAMURA TATSUHIKO , NAGATOMO KENICHI
IPC分类号： H04Q3/00 , H04L12/28 , H04L12/70 , H04L12/931 , H04L12/937 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To easily perform mediation when selective broadcast to a packet (cell) is requested with simple constitution in the case of providing an input buffer for tentatively storing the packet (cell) for each incoming line and mediating the packets of the same destination prior to the exchange of the packet. SOLUTION: The decoded result of decoders 520-523 is supplied to a selective broadcast request butter mediation circuit 53MC of a competing cell mediation circuit 53 and the selective broadcast request buffer mediation circuit 53MC mediates one of the plural input buffers 300-303 (selective broadcast request buffers) provided with an output request to optional plural outgoing lines (2-all lines or all lines -1). A mediated result is returned to all the decoders 520-523.

2. 发明专利

JPH06311542A SELF-ROUTING SWITCH AND EXCHANGE USING THE SAME 失效
公开(公告)号：JPH06311542A
公开(公告)日：1994-11-04
申请号：JP9321493
申请日：1993-04-20
申请人： OKI ELECTRIC IND CO LTD
发明人： KITAMURA TATSUHIKO , HAGIO MASAMI
IPC分类号： H04Q3/52 , H04Q11/04 , H04L12/48
摘要： PURPOSE:To eliminate the need for synchronization between a FIFO and a switch LSI and to reduce a cell arbitration time by integrating an input buffer into the switch LSI and arranging the FIFO to a pre-stage of the switch LSI. CONSTITUTION:A cell 100 is inputted to ax FIFO 2. The FIFO 2 sends the cell 100 to a switch LSI 1 when an output enable OE signal from a post-stage switch LSI 1 is set. The sent cell 100 is stored in the switch LSI 1 in the switch LSI. Cells are adjusted by the survival method between an input buffer 12 and a negotiation network 14. The input buffer 12 receiving a survival report outputs the cell 100 to an exchange network 16. The arbitration of the cells is executed in the LSI 1 in this way. Moreover, no cell is outputted from the input buffer 12 not receiving the survival report in the cell arbitration. Thus, when it takes consecutively in the same buffer 12, the cells are fully stored in the buffer 12 (input buffer full).

3. 发明专利

JPH04179339A PRIORITY CONTROL SYSTEM FOR EXCHANGE 失效
公开(公告)号：JPH04179339A
公开(公告)日：1992-06-26
申请号：JP30604990
申请日：1990-11-14
申请人： OKI ELECTRIC IND CO LTD
发明人： NOIRI AKIRA , ARAKAWA NOBUYA , KITAMURA TATSUHIKO , KIMURA HIROSHI
摘要： PURPOSE:To supress the occurrence of a state where data is excessively accumulated in a corresponding buffer memory by abolishing a cell without accumulation when data on a bit rate exceeding a report value is inputted from a terminal and the empty area of the buffer memory in a cell buffer circuit is comparatively little. CONSTITUTION:When the bit rate of reception data exceed the report value, a bit rate detection circuit 52 adds information showing the effect to reception data so as to mark it. A header update circuit 70 sets marked reception data and reception data instructed as nonpriority data to be abolishment possible data by giving information showing abolishment is possible to a header. An accumulation judgement circuit 81 judges whether reception data is to be accumulated or not based on abolishment possible information and a data amount accumulated in the buffer memory 82. When the abolishment of data is judged, reception data is abolished. Thus, the abolishment rate of reception data with other priority is suppressed.

4. 发明专利

JPH1175227A DATA COMMUNICATION DEVICE 失效
公开(公告)号：JPH1175227A
公开(公告)日：1999-03-16
申请号：JP23389397
申请日：1997-08-29
申请人： OKI ELECTRIC IND CO LTD
发明人： KITAMURA TATSUHIKO
IPC分类号： H04Q3/545
摘要： PROBLEM TO BE SOLVED: To decrease the number of connections between 1st and 2nd substrates by storing transfer information outputted in parallel from a 1st CPU on a 1st substrate, and converting the transfer information into serial data with a 1st transmission instruction from the 1st CPU and sending the data to a 2nd CPU on a 2nd substrate when the stored transfer information reaches a predetermined prescribed amount. SOLUTION: The CPU 101A writes the information to be sent in a transmitting memory 103A in parallel and outputs the transmission instruction to a control register control circuit 102A when the written information reaches the prescribed amount. The control register control circuit 102A controls the transmitting memory 103A and a parallel-serial conversion part 104A to convert the information in the transmitting memory 103A into serial data, which are sent to the substrate B. The substrate B converts the information sent from the substrate A into parallel data by a serial-parallel conversion part 106B. Consequently, the frequency at which the CPU 101 outputs the transmission instruction can be decreased and a serial communication is enabled.

5. 发明专利

JPH06169496A CALL ACCEPTANCE CONTROL SYSTEM FOR ATM SWITCH 失效
公开(公告)号：JPH06169496A
公开(公告)日：1994-06-14
申请号：JP7298291
申请日：1991-04-05
申请人： OKI ELECTRIC IND CO LTD
发明人： KITAMURA TATSUHIKO , ARAKAWA NOBUYA , NOIRI AKIRA , WATANABE TAKASHI
IPC分类号： H04Q3/52 , H04Q11/04 , H04L12/48
摘要： PURPOSE:To provide the call acceptance control system which is suitable to an input buffer type ATM switch add secures a required communication quality. CONSTITUTION:A band management table 54a and a buffer management table 54b at every call classification where the use volume sufficiently satisfying a required communication quality is corresponded to the number of calls to be simultaneously connected are prepared. The use volume which will be increased at the time of accepting a new call is predicted based on these management tables with respect to the respective incoming line bands to input buffers 53 and a switch main body 52 and outgoing line bands from the switch main body 52. The use volume of the sum of the present use volume and the predictive increase use volume is compared with a threshold to discriminate whether the new call should be accepted or not.

6. 发明专利

JPH04310879A DEVICE INTERFACE CIRCUIT 失效
公开(公告)号：JPH04310879A
公开(公告)日：1992-11-02
申请号：JP7772991
申请日：1991-04-10
申请人： OKI ELECTRIC IND CO LTD
发明人： WATANABE TAKASHI , NOIRI AKIRA , KITAMURA TATSUHIKO , ARAKAWA NOBUYA
IPC分类号： G01R31/28 , G06F11/22 , H03K19/0175
摘要： PURPOSE:To easily detect a wiring trouble place at the time of circuit test/ adjustment and to avoid system-down in the case of wiring trouble handled as partial functional trouble at the time of actual use. CONSTITUTION:A device interface circuit has a first output means 10, 30 outputting a received signal as it is without changing the polarity thereof, second output means 12, 32 reversing the polarity of the received signal to output said signal and the selection means 13, 34 connected to the output sides of the first output means 10, 30 and the second output means 12, 32 and selectively outputting the signal outputted from either one of those means according to indication.

7. 发明专利

JPH04123128A MAXIMUM VALUE/MINIMUM VALUE DETECTING SORTER 失效
公开(公告)号：JPH04123128A
公开(公告)日：1992-04-23
申请号：JP24128990
申请日：1990-09-13
申请人： OKI ELECTRIC IND CO LTD
发明人： HAYASHI KENTARO , NOIRI AKIRA , KITAMURA TATSUHIKO , UETAKE YOSHIKATSU
IPC分类号： G06F7/02 , G06F7/06
摘要： PURPOSE:To decrease the hardware quantity and to extract the data of the maximum value and the minimum value from in the inputted data at a high speed by executing the multistage connection of switch element so as to sort the data of the maximum value and the data of the minimum data to an output terminal of a sorter, from in plural input data. CONSTITUTION:As for plural binary data inputted to input terminals 100 to 107, first of all, whether the data are large or small is compared by switches 10-00 to 10-03 being switches of a first stage, and large data and small data are outputted to an output terminal of the upper side and and output terminal of the lower side, respectively, and sent to switches 10-10 to 10-13 of a second stage. In the same way, a switch 10-20 executes a comparison of input data, large data in the inputted data is switched to an output terminal 200, and data of the maximum value in the data inputted to a sorter 1 is outputted from the output terminal 200. Also, by a switch 10-21, a comparison of the input data is executed, and the minimum data in the input data is outputted to an output terminal 201. In such a way, the hardware quantity can be curtailed and the sorting time can be shortened.

8. 发明专利

JPH06224935A CELL EXCHANGE DEVICE 失效
公开(公告)号：JPH06224935A
公开(公告)日：1994-08-12
申请号：JP1234093
申请日：1993-01-28
申请人： OKI ELECTRIC IND CO LTD
发明人： HAGIO MASAMI , KITAMURA TATSUHIKO , NOIRI AKIRA
IPC分类号： H04Q11/04 , H04L12/48
摘要： PURPOSE:To obtain the output buffer type cell exchange device not requiring a high speed output buffer and a high speed TD bus regardless of the presence of lots of input line numbers. CONSTITUTION:Cells received from incoming lines 211-214 are tentatively stored in relevant input buffers A1-A4 and outputted one by one synchronously with a cell exchange period. In this case, when lots of cells whose destination is the same are in existence, cells of a prescribed number K are outputted among the contention cells and the remaining cells are kept waiting in the buffers. The cells outputted from the input buffers A1-A4 are shared to outgoing lines 241-244 in response to the destination by address filters B1-B4 of cell output circuits 231-234. Cells of K-sets at maximum shared to each outgoing line 24n are subject to time division multiplexing by a K:1 cell multiplexer circuit B5 and the result is outputted one by one from an output buffer B6 synchronously with a cell exchange period.

9. 发明专利

JPH05227194A BUFFER READING SYSTEM 失效
公开(公告)号：JPH05227194A
公开(公告)日：1993-09-03
申请号：JP2926292
申请日：1992-02-17
申请人： OKI ELECTRIC IND CO LTD
发明人： NOIRI AKIRA , OKAMOTO YASUSHI , KITAMURA TATSUHIKO , WATANABE TAKASHI
IPC分类号： H04L13/08
摘要： PURPOSE:To improve the utilizing efficiency of buffers to which data is inputted asynchronously and the stored data is successively read out at the lowest data abolition ratio. CONSTITUTION:Buffers 11-in store data inputted from input lines 21 to 2n. A scheduler 33 detects the data amount of the buffers 11 to 1n. Normally, the maximum value of buffers showing the maximum value of the storage data amount from among the buffers 11 to 1n is less than the prescribed threshold value, the scheduler 33 gives a direction reading the storage data out from buffers 11 to 1n in the order stored by the prescribed amount in the prescribed cycle. When the maximum value of the storage data amount exceeds the threshold value in the buffer showing the maximum value of the storage data amount, the scheduler 33 gives a direction to increase the number of reading data of the buffer showing the maximum value to a buffer reading circuit 31.

10. 发明专利

JPH04196846A HEADER CONVERTER AND SWITCHBOARD USING THIS DEVICE 失效
公开(公告)号：JPH04196846A
公开(公告)日：1992-07-16
申请号：JP32330690
申请日：1990-11-28
申请人： OKI ELECTRIC IND CO LTD
发明人： KIMURA HIROSHI , ARAKAWA NOBUYA , KITAMURA TATSUHIKO , HAGIO MASAMI
IPC分类号： H04L12/28
摘要： PURPOSE:To enable a VC service and a VP service by one ATM switch by providing both a selecting means, and a control means which judges one of the VP/VC services, and controls the switching of a header, based on identified information, inputted from an identifying means. CONSTITUTION:When a cell 100 is inputted from a cell input terminal 1, transmitting VPI information and transmitting VCI information in the cell 100 is latched by a VPI/VCI latch circuit 3. The latched transmitting VPI information is applied to a VP/VC service identifying barrel memory 4 as an address. The VP/VC service information preliminarily set for each VPI is read from the VP/VC service identifying barrel memory 4 by this address information. Then, this VP/VC service information 15 is transmitted to SEL I and SEL I switching control circuit 8, as SEL I and SEL II switching information. Thus, both the services can be offered by one ATM switch.

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