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1. 发明专利

JP2008041907A Ld differential drive circuit 审中-公开
标题翻译： LD差分驱动电路
公开(公告)号：JP2008041907A
公开(公告)日：2008-02-21
申请号：JP2006213732
申请日：2006-08-04
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： TOGASHI MINORU , UMEDA YOTARO , OTOMO YUSUKE , NAKAMURA MAKOTO , KAWAMURA TOMOAKI , ENDO JUN , TERADA JUN , NISHIMURA KAZUYOSHI , AKATSU YUJI , ENDO MASAHIRO
IPC分类号： H01S5/0683 , H03F3/45 , H04B10/07 , H04B10/2507 , H04B10/293 , H04B10/40 , H04B10/50 , H04B10/516 , H04B10/564 , H04B10/572 , H04B10/60
摘要： PROBLEM TO BE SOLVED: To reduce the jitter of a current flowing through a laser diode.
SOLUTION: An LD differential drive circuit comprises an LD drive circuit 10 having differential output terminals OUT1, OUT2 oututting an LD drive current and an LD bias terminal BB outputting an LD bias current, a transmission line T1 connected between one terminal of a laser diode LD and the output terminal OUT1, a transmission line T2 connected between the other terminal of the laser diode LD and the output terminal OUT2, a bias inductor L1 connected between one terminal of the laser diode LD and an LD power supply terminal VCC2, and a bias resistor R6 connected between the other terminal of the laser diode LD and the LD bias terminal BB.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：减少流过激光二极管的电流的抖动。解决方案：LD差分驱动电路包括具有输出LD驱动电流的差分输出端OUT1，OUT2和输出LD偏置电流的LD偏置端BB的LD驱动电路10，连接在一端激光二极管LD和输出端子OUT1，连接在激光二极管LD的另一个端子和输出端子OUT2之间的传输线T2，连接在激光二极管LD的一个端子和LD电源端子VCC2之间的偏置电感器L1，以及连接在激光二极管LD的另一个端子和LD偏置端子BB之间的偏置电阻器R6。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007036329A Amplifier circuit and transimpedance amplifier 审中-公开
标题翻译：放大器电路和放大放大器
公开(公告)号：JP2007036329A
公开(公告)日：2007-02-08
申请号：JP2005212322
申请日：2005-07-22
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NAKAMURA MAKOTO , UMEDA YOTARO , ENDO JUN , AKATSU YUJI , HYODO EIJI , KAYANO EMIKO , IIZUKA HATSUSHI , URABE YOSHIKAZU , JIYUUBAYASHI MASATOSHI
IPC分类号： H03F3/08 , H03F3/34 , H03G3/10
摘要： PROBLEM TO BE SOLVED: To obtain a flat frequency characteristic having no excessive peaking even if a gain is switched with respect to a variable gain type amplifier to be used for an optical reception circuit.
SOLUTION: A current source circuit 3 is connected to an output terminal OUTa of an emitter grounding circuit 1A outputting an amplification signal S, and a bias current to be supplied to an input stage transistor of the emitter grounding circuit 1A is shunted to the current source circuit 3. In this case, the size of the current to be shunted is controlled in accordance with the gain of the amplifier circuit 10A selected in a gain switching circuit 20.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使相对于用于光接收电路的可变增益型放大器切换增益，也可以获得没有过度峰值的平坦频率特性。
解决方案：电流源电路3连接到输出放大信号S的发射极接地电路1A的输出端OUTa，并且提供给发射极接地电路1A的输入级晶体管的偏置电流被分流到电流源电路3.在这种情况下，根据在增益切换电路20中选择的放大器电路10A的增益来控制待分路电流的大小。（C）2007，JPO＆INPIT

3. 发明专利

JP2006337727A Optical transceiver and its latch mechanism 有权
标题翻译：光学收发器及其锁定机构
公开(公告)号：JP2006337727A
公开(公告)日：2006-12-14
申请号：JP2005162485
申请日：2005-06-02
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： UMEDA YOTARO , NAKAMURA MAKOTO , ENDO JUN , AKATSU YUJI , NAKANO JUNICHIRO , KITAHARA KOJI
IPC分类号： G02B6/42 , H01L31/12
摘要： PROBLEM TO BE SOLVED: To facilitate a taking-out operation by consolidating an operation for releasing the engaged state of a locking means and an operation for taking out an optical transceiver from a cage into one essentially continuous operation. SOLUTION: An elastic piece 7 having a locking hole 6 is installed in a cage 2 on communication equipment side. A locking part 17, a latch releasing lever 37, and an operating lever 38 are installed in an optical transceiver 4. The latch releasing lever 37 is assembled freely movably forwards and backwards in a receptacle 11, with the front and rear ends projecting outward. The operating lever 38 is provided freely rotatably on the outside of the receptacle 11, actuating the latch releasing lever 37 by being rotated by a force in the direction of taking out the optical transceiver 4 from the cage 2, when the engaged state is released between the locking hole 6 and the locking part 17. Thus, the latch releasing lever 37 is moved to the rear, with the elastic piece 7 elastically deformed downward by a lock releasing part 37C provided to the rear end, thereby releasing the engaged state between the locking hole 6 and the locking part 17. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过整合用于释放锁定装置的接合状态的操作和将光收发器从保持架取出的操作进入一个基本上连续的操作来促进取出操作。解决方案：具有锁定孔6的弹性件7安装在通信设备侧的保持架2中。锁定部件17，闩锁释放杆37和操作杆38安装在光学收发器4中。闩锁释放杆37可随意地前后移动地容纳在插座11中，前端和后端向外突出。操作杆38可自由旋转地设置在容器11的外侧上，当接合状态被释放在保持器2之间时，通过从取下光收发器4的方向转动的力来驱动闩锁释放杆37。锁定孔6和锁定部17.因此，闩锁释放杆37向后移动，弹性片7通过设置在后端的锁定释放部37C而向下弹性变形，从而释放接合状态锁定孔6和锁定部分17.版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2008041902A Ld drive circuit 审中-公开
标题翻译： LD驱动电路
公开(公告)号：JP2008041902A
公开(公告)日：2008-02-21
申请号：JP2006213650
申请日：2006-08-04
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： TOGASHI MINORU , UMEDA YOTARO , OTOMO YUSUKE , NAKAMURA MAKOTO , KAWAMURA TOMOAKI , ENDO JUN , TERADA JUN , NISHIMURA KAZUYOSHI , AKATSU YUJI , ENDO MASAHIRO
IPC分类号： H01S5/062 , H04B10/2507 , H04B10/40 , H04B10/50 , H04B10/516 , H04B10/60
摘要： PROBLEM TO BE SOLVED: To prevent the impairment of output waveform from an LD drive circuit.
SOLUTION: The LD drive circuit comprises a differential circuit consisting of transistors Q1 and Q2, a load resistor R1 connected between the collector of the transistor Q1 and a power supply terminal VCC, a load resistor R2 connected between the collector of the transistor Q2 and the power supply terminal VCC, and a power supply transistor Q3 and a current stabilization resistor R3 connected in series between the emitters of the transistors Q1, Q2 and the ground terminal GND. The bases of the transistors Q1 and Q2 are connected with the differential input terminals IN1 and IN2, and the collectors of the transistors Q1 and Q2 are connected with the differential output terminals OUT1 and OUT2. In such an LD drive circuit, a power supply stabilization capacitor C1 having a capacitance of at least 10 pF is connected between the power supply terminal VCC and the ground terminal GND.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止LD驱动电路的输出波形的损害。解决方案：LD驱动电路包括由晶体管Q1和Q2组成的差分电路，连接在晶体管Q1的集电极和电源端VCC之间的负载电阻R1，连接在晶体管Q1的集电极之间的负载电阻R2 Q2和电源端子VCC，以及串联连接在晶体管Q1，Q2的发射极和接地端子GND之间的电源晶体管Q3和电流稳定电阻器R3。晶体管Q1和Q2的基极与差分输入端IN1和IN2连接，晶体管Q1和Q2的集电极与差分输出端OUT1和OUT2连接。在这种LD驱动电路中，在电源端子VCC和接地端子GND之间连接具有至少10pF的电容的电源稳定电容器C1。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006311212A Level holding circuit 有权
标题翻译：电平保持电路
公开(公告)号：JP2006311212A
公开(公告)日：2006-11-09
申请号：JP2005131400
申请日：2005-04-28
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NAKAMURA MAKOTO , UMEDA YOTARO , ENDO JUN , AKATSU YUJI , IMAI YUUKI , JIYUUBAYASHI MASATOSHI , URABE YOSHIKAZU , IIZUKA HATSUSHI
IPC分类号： H03K17/00 , H03F3/10 , H03F3/45 , H03G3/20 , H04B10/07 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/69
摘要： PROBLEM TO BE SOLVED: To provide a level holding circuit capable of a high-speed response with fewer ripples of an output voltage.
SOLUTION: The level holding circuit is provided with a buffer amplifier circuit 1 wherein signals are inputted to a noninverted input terminal 5, and two holding circuit parts 2 and 3 whose input terminal is connected to the output terminal 7 of the buffer amplifier circuit 1 and which hold the maximum value or minimum value of signals outputted from the output terminal 7. The output terminal of the first holding circuit part 2 is connected to the reference voltage input terminal 6 of the buffer amplifier circuit 1, and the output terminal of the second holding circuit part 3 is connected to a signal output terminal 9.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够以较少的输出电压纹波进行高速响应的电平保持电路。电平保持电路设置有缓冲放大器电路1，其中信号被输入到非反相输入端子5，以及两个保持电路部分2和3，其输入端连接到缓冲放大器的输出端子7 电路1，并且保持从输出端子7输出的信号的最大值或最小值。第一保持电路部分2的输出端子连接到缓冲放大器电路1的参考电压输入端子6，输出端子第二保持电路部分3连接到信号输出端子9.版权所有：（C）2007，JPO＆INPIT

6. 发明专利

JP2008072440A Limiter amplifier circuit 审中-公开
标题翻译：限幅放大器电路
公开(公告)号：JP2008072440A
公开(公告)日：2008-03-27
申请号：JP2006249117
申请日：2006-09-14
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NAKAMURA MAKOTO , UMEDA YOTARO , ENDO JUN , AKATSU YUJI , IMAI YUUKI , JIYUUBAYASHI MASATOSHI , URABE YOSHIKAZU , IIZUKA HATSUSHI
IPC分类号： H03G11/00 , H03F3/08 , H03F3/34 , H03F3/45 , H03K5/08
摘要： PROBLEM TO BE SOLVED: To provide a limiter amplifier circuit which can obtain satisfactory common mode noise resistant and performs a high-speed response to an input signal. SOLUTION: The limiter amplifier circuit has a differential amplifier 2 for amplifying an input signal of a differential form comprising a positive phase input signal VIP and a negative phase input signal VIN, and an offset compensation circuit (AOC circuit 3) for extracting current corresponding to a voltage difference between a maximum value of the positive phase input signal VIP and a maximum value of the negative phase input signal VIN from a pair of load resistors 24 and 25 of a differential circuit provided in an input stage of a differential amplifier 2. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以获得令人满意的共模噪声并对输入信号执行高速响应的限幅放大器电路。
解决方案：限幅放大器电路具有用于放大包括正相输入信号VIP和负相输入信号VIN的差分形式的输入信号的差分放大器2和用于提取的偏移补偿电路（AOC电路3）对应于正相输入信号VIP的最大值之间的电压差和来自设置在差分放大器的输入级中的差分电路的一对负载电阻器24和25的负相位输入信号VIN的最大值的电流 2.版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007005968A Detection circuit for burst-head 有权
标题翻译：针刺头检测电路
公开(公告)号：JP2007005968A
公开(公告)日：2007-01-11
申请号：JP2005181648
申请日：2005-06-22
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NAKAMURA MAKOTO , UMEDA YOTARO , ENDO JUN , AKATSU YUJI , IIZUKA HATSUSHI , URABE YOSHIKAZU , JIYUUBAYASHI MASATOSHI
IPC分类号： H04L7/10 , H03G11/04 , H04B10/272 , H04B10/40 , H04B10/50 , H04B10/524 , H04B10/58 , H04B10/60 , H04L25/06
摘要： PROBLEM TO BE SOLVED: To eliminate noise for a non-signal period between burst signals by detecting the head of the burst signal.
SOLUTION: A detection circuit for burst-head includes: a high pass filter 3 for receiving burst signals AOP, AON, a hysteresis comparator 4 that receives filter output signals HOP, HON passing through the high pass filter 3 to detect a change in the filter output signals whose level exceeds a prescribed threshold value; and a switch 6 that shuts-off the output of the burst signals to post-stage circuits until the hysteresis comparator 4 detects the head of the burst signal and outputs the burst signals to the post-stage circuits when the hysteresis comparator 4 detects the head of the burst signal.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过检测突发信号的头部来消除突发信号之间的非信号周期的噪声。解决方案：用于脉冲串头的检测电路包括：高通滤波器3，用于接收脉冲串信号AOP，AON，磁滞比较器4，其接收通过高通滤波器3的滤波器输出信号HOP，HON，以检测变化在其电平超过规定阈值的滤波器输出信号中; 以及开关6，其将突发信号的输出截断到后级电路，直到滞后比较器4检测到脉冲串信号的头部，并且当磁滞比较器4检测到磁头时将脉冲串信号输出到后级电路的突发信号。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2006311030A Transimpedance amplifier 有权
标题翻译：转移放大器
公开(公告)号：JP2006311030A
公开(公告)日：2006-11-09
申请号：JP2005129199
申请日：2005-04-27
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NAKAMURA MAKOTO , UMEDA YOTARO , ENDO JUN , AKATSU YUJI , JIYUUBAYASHI MASATOSHI , URABE YOSHIKAZU , HYODO EIJI
IPC分类号： H03F3/08 , H03G3/20 , H03G3/30
摘要： PROBLEM TO BE SOLVED: To achieve high sensitivity and a wide input dynamic range, instantaneous response corresponding to burst data, and operational stability against noise. SOLUTION: A gain switching determination circuit 250 outputs a gain switching signal SEL based on the comparison result of a comparison input voltage Vc, i.e. a differential output signal from an intermediate stage buffer circuit 230, and first hysteresis characteristics, and performs operation for switching gains of first and second transimpedance amplifier core circuits 210 and 220. A filter circuit 223 reduces a high frequency band in the frequency characteristics of the second transimpedance amplifier core circuit 220. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：实现高灵敏度和宽输入动态范围，对应于突发数据的瞬时响应以及抗噪声的操作稳定性。解决方案：增益切换确定电路250基于比较输入电压Vc的比较结果（即来自中间级缓冲电路230的差分输出信号）和第一滞后特性来输出增益切换信号SEL，并执行操作用于切换第一和第二跨阻放大器核心电路210和220的增益。滤波器电路223减少第二跨阻放大器核心电路220的频率特性中的高频带。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2007036328A Transimpedance amplifier 有权
标题翻译：转移放大器
公开(公告)号：JP2007036328A
公开(公告)日：2007-02-08
申请号：JP2005212319
申请日：2005-07-22
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NAKAMURA MAKOTO , UMEDA YOTARO , ENDO JUN , AKATSU YUJI , HYODO EIJI , KAYANO EMIKO , IIZUKA HATSUSHI , URABE YOSHIKAZU , JIYUUBAYASHI MASATOSHI
IPC分类号： H03F3/34 , H03F3/08 , H03G3/20
摘要： PROBLEM TO BE SOLVED: To stably obtain an output signal with a sufficient amplitude even if an input current is attenuated in order to deal with an input current of a wide dynamic range in an optical reception circuit.
SOLUTION: A gain switching determining circuit 250 reduces the gains of first and second transimpedance core circuits 210, 220. After that, when a comparing input voltage Vc is reduced to a predetermined reset voltage Vr, a reset determining circuit 260 outputs a reset signal RESET for resetting a gain switching operation of the determining circuit 250 to initialize the gain.
COPYRIGHT: (C)2007,JPO&INPIT

10. 发明专利

JP2006311210A Limiter amplifier circuit 有权
标题翻译：限幅放大器电路
公开(公告)号：JP2006311210A
公开(公告)日：2006-11-09
申请号：JP2005131393
申请日：2005-04-28
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NAKAMURA MAKOTO , UMEDA YOTARO , ENDO JUN , AKATSU YUJI , IMAI YUUKI , JIYUUBAYASHI MASATOSHI , URABE YOSHIKAZU , IIZUKA HATSUSHI
IPC分类号： H03F3/34 , H03F3/08 , H03F3/16 , H03F3/45
摘要： PROBLEM TO BE SOLVED: To provide a limiter amplifier circuit in which a favorable common mode noise tolerance is attained and a high speed response to an input signal is ensured.
SOLUTION: The limiter amplifier circuit comprises a differential amplifier 2 for amplifying a differential input signal composed of a positive-phase input signal VIP and a negative-phase input signal VIN, and an AOC circuit 3 for drawing out a current corresponding to the voltage difference of a maximum value between the positive-phase input signal VIP and the negative-phase input signal VIN from a pair of load resistors 24 and 25 provided on the input stage of the differential amplifier 2.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种限制器放大器电路，其中获得良好的共模噪声容限并确保对输入信号的高速响应。解决方案：限幅放大器电路包括用于放大由正相输入信号VIP和负相输入信号VIN组成的差分输入信号的差动放大器2，以及AOC电路3，用于绘制对应于来自设在差分放大器2的输入级上的一对负载电阻器24和25的正相输入信号VIP和负相输入信号VIN之间的最大值的电压差。版权所有（C））2007，JPO＆INPIT

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