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1. 发明专利

JPS58212266A Offset voltage control circuit for television signal 失效
标题翻译：电视信号偏置电压控制电路
公开(公告)号：JPS58212266A
公开(公告)日：1983-12-09
申请号：JP9554082
申请日：1982-06-03
申请人： Nec Corp , Nec Eng Ltd
发明人： IIJIMA MASAHIKO , KOBAYASHI SADAMU
IPC分类号： H04N5/18 , H04N5/16
CPC分类号： H04N5/16
摘要： PURPOSE:To attain restoration to the normal operating state in a short time when a voltage correcting signal having an excessive amplitude is generated, by providing a means limiting the range of amplitude of the voltage correcting signal. CONSTITUTION:A voltage given from an integration circuit 13 is impressed to voltage comparison circuits 25, 26 of a correcting voltage limit circuit 14 and also to an offset voltage correcting circuit 11. The circuit 25 (26) compares a voltage of a signal received from the circuit 13 with a reference voltage V1 (V2), and when the former is higher (lower), a signal of H level is given to a switch circuit 27 (28) as a switching signal and when lower (higher), a signal of L level. The circuit 27 (28) keeps a voltage V3 (V4) set lower (higher) than the voltage V1 (V2) when the received signal is H level, and interrupts the voltage V3 (V4) when L level. When the circuits 27, 28 are interrupted, the signal transmitted from the circuit 13 is given to the circuit 11 as it is. When one of the circuits 27, 28 is in connecting state, the voltage of the circuit 13 is reset forcedly into an amplitude within the voltage limit range.
摘要翻译：目的：通过提供限制电压校正信号的幅度范围的装置，通过产生具有过大振幅的电压校正信号，在短时间内恢复正常工作状态。构成：从积分电路13给出的电压被施加到校正电压限制电路14的电压比较电路25,26以及偏移电压校正电路11.电路25（26）比较从具有参考电压V1（V2）的电路13，并且当前者较高（较低）时，H电平的信号作为开关信号被提供给开关电路27（28），并且当较低（较高）时，信号的L级。当接收信号为H电平时，电路27（28）将电压V3（V4）设置为低于电压V1（V2），当L电平时中断电压V3（V4）。当电路27,28被中断时，从电路13发送的信号被原封不动地给予电路11。当电路27,28中的一个处于连接状态时，电路13的电压被强制地复位到电压极限范围内的幅度。

2. 发明专利

JPS62245869A SYNCHRONIZING SEPARATOR CIRCUIT 失效
公开(公告)号：JPS62245869A
公开(公告)日：1987-10-27
申请号：JP8809586
申请日：1986-04-18
申请人： NEC CORP , NIPPON ELECTRIC ENG
发明人： IIJIMA MASAHIKO , NOHARA TAKUYA , OSHIMA TOSHIO
IPC分类号： H04N5/08
摘要： PURPOSE:To accurately sxtract a synchronizing signal from a signal superim posed with a periodic synchronizing signal by providing a time width detector detecting a waveform pattern except the time width of a synchronizing signal, a pattern detection inhibition pulse generating section and a gate circuit. CONSTITUTION:The harmonic and the chroma components of an input color television signal are suppressed by an input filter 2, a voltage comparator 3 detects the waveform of predetermined voltage, and a time width detector 4 detects a signal smaller than the time width of a synchronizing signal. A pulse generating section 5 uses the output of the detector 4 to generate a pattern detection inhibiting pulse having a predetermined inhibition time width, and whether or not the output of the detector 4 is generated from the same output as that of the voltage comparator 3 generating the pattern detection inhibition pulse is discriminated and when the output comes from the same output of the voltage comparator 3, the generation of the pattern detection inhibition pulse is inhibited. A gate circuit 6 ANDs the output of the voltage comparator 3 and the pattern detection inhibition pulse and outputs the result from an output terminal 19 as a synchronizing signal.

3. 发明专利

JPS59161745A Fault diagnostic device 失效
标题翻译：故障诊断装置
公开(公告)号：JPS59161745A
公开(公告)日：1984-09-12
申请号：JP3593283
申请日：1983-03-07
申请人： Nec Corp
发明人： IIJIMA MASAHIKO
IPC分类号： G06F11/22 , G06F11/273
CPC分类号： G06F11/273
摘要： PURPOSE:To decide on whether a fault occurs to each signal processing block or not by supplying a test signal for fault search to digital signal processing blocks having the same functions and deciding on whether their processing results are coincident or not. CONSTITUTION:A fault diagnosis of, for example, signal processing blocks 12, 22, and 32 is used. Switches 14, 24, and 34 of digital signal processors 10, 20, and 30 are thrown to sides B; switches 16, 26, and 36 are thrown to sides A; and switches 17, 27, and 37 are thrown to sides B. In this state, the test signal is supplied from a test signal generating circuit 41 to the signal processors 10, 20, and 30 through a signal line 101. Consequently, in a coincidence circuit 42, all processed results of the processing blocks 12, 22, and 32 are made coincident when they are normal, or dissident when a fault occurs to some block. The respective switches are controlled on the basis of the output of the circuit 42 to decide on the fault occurrence for a combination of signal processing blocks 11, 21, and 31 and a combination of 13, 23, and 33.
摘要翻译：目的：通过向具有相同功能的数字信号处理模块提供故障搜索的测试信号，并确定其处理结果是否一致，来决定每个信号处理块是否发生故障。构成：使用例如信号处理块12,22和32的故障诊断。数字信号处理器10,20和30的开关14,24和34被投掷到侧面B; 开关16,26和36被抛到侧面A上; 并且开关17,27和37被投掷到侧面B.在这种状态下，测试信号通过信号线101从测试信号发生电路41提供给信号处理器10,20和30.因此，在一致电路42，处理块12,22和32的所有处理结果在它们正常时被重合，或者当某个块发生故障时不稳定。基于电路42的输出来控制各个开关，以决定信号处理块11,21和31的组合以及13,23和33的组合的故障发生。

4. 发明专利

JPS63126331A INPUT SIGNAL SWITCHING CIRCUIT 失效
公开(公告)号：JPS63126331A
公开(公告)日：1988-05-30
申请号：JP27190486
申请日：1986-11-17
申请人： NEC CORP , MIYAGI NIPPON DENKI KK
发明人： SHIBUYA TORU , IIJIMA MASAHIKO
IPC分类号： H04J3/08
摘要： PURPOSE:To prevent malfunction due to external noise by providing a frame synchronizing detection circuit so as to switch an input such as a PCM primary group data signal with priority. CONSTITUTION:A digital voice input signal at a terminal 1 is fed to a multiplex circuit 5 via a switch 4. When a DSI (PCM primary group) data signal is inputted to a terminal 2, a frame synchronizing detection circuit 3 detects it to change over the switch 4 to supply the DS 1 signal to the multiplexer 5. That is, only when the 2nd signal is inputted correctly to the terminal 2, the circuit 3 detects the 2nd signal and the output signal representing the result of detection switches the switch 4 to the position of the terminal 2.

5. 发明专利

JPS61114678A Prediction coding device for image signal 失效
标题翻译：图像信号预测编码装置
公开(公告)号：JPS61114678A
公开(公告)日：1986-06-02
申请号：JP23622884
申请日：1984-11-09
申请人： Nec Corp , Nippon Telegr & Teleph Corp
发明人： IINUMA KAZUMOTO , IIJIMA MASAHIKO , KURODA HIDEO , HASHIMOTO HIDEO
IPC分类号： H04N19/50 , G06T9/00
CPC分类号： H04N19/593 , H04N19/503 , H04N19/51
摘要： PURPOSE:To device simplification of code processing with respect to fraction by establishing means for setting the prediction signal and the predicted error signal in the prediction code part over the preliminarily fixed value in regard to fractional picture element block caused by the two-dimensional block. CONSTITUTION:Output of selection circuit 12 is provided to the adding machine 13 to calculate the sum with the output of selection circuit 15. The result is provided to the prediction circuit 14 and D/A convertor 16. In the prediction circuit 14 the predicted function is calculated by the same predicted function as the prediction circuit 7 at the prediction code part. The result is provided to the selection circuit 15. Further, in the prediction circuit 14, the predicted value compensated by movement based on the 2nd dimensional block unit is calculated by the moving vector provided by transfer lane code circuit 10. In the selection circuit 15, either of the prediction signal which is the output of the prediction circuit 14 or of the preliminarily fixed value A is selected to provide its output to the adding machine 13.
摘要翻译：目的：通过建立用于在由二维块引起的关于分数像素块的预先确定的值上设置预测编码部分中的预测信号和预测误差信号的装置来简化关于分数的代码处理。构成：选择电路12的输出被提供给加法器13，以与选择电路15的输出计算和。结果被提供给预测电路14和D / A转换器16.在预测电路14中，预测功能通过与预测代码部分的预测电路7相同的预测功能来计算。结果被提供给选择电路15.此外，在预测电路14中，通过由传送车道编码电路10提供的移动矢量来计算基于二维块单位的移动补偿的预测值。在选择电路15 选择作为预测电路14的输出的预测信号或预先确定的值A中的任一个，以将其输出提供给加法机13。

6. 发明专利

JPH02206982A CODING METHOD FOR MOVING PICTURE SIGNAL 失效
公开(公告)号：JPH02206982A
公开(公告)日：1990-08-16
申请号：JP2653089
申请日：1989-02-07
申请人： NEC CORP
发明人： OKI JUNICHI , IIJIMA MASAHIKO
IPC分类号： H04N19/00 , H04B14/04 , H04N19/423 , H04N19/436 , H04N19/503 , H04N19/587 , H04N19/593 , H04N19/70
摘要： PURPOSE:To eliminate the need for a buffer memory for an output of a coder by advancing the coding by n-line each while being in response to the speed of a transmission line through the use of a moving picture signal processing processor and giving a command of coding a succeeding frame when the coding of a predetermined line is finished and the output is given. CONSTITUTION:The system is used, which comprises unit processors A1-An for processing a moving picture signal, a frame memory 4, an input bus 5, feedback buses 6, 7, an output bus 8, an input signal (a), an output signal (b) and a transmission line clock (c). Then one pattern of moving picture signals is stored in response to the command of coding execution, the picture stored in response to the speed of the transmission line is coded by n-line each and after the coding of a predetermined line in the screen is finished, a command of execution of new coding is given. Thus, no buffer memory is required for the output of the coder and a delay in the coded picture having been caused due to the buffer memory is not produced.

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