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1. 发明专利

JP2013211447A Silicon carbide vertical mosfet and manufacturing method of the same 有权
标题翻译：硅碳化钨垂直MOSFET及其制造方法
公开(公告)号：JP2013211447A
公开(公告)日：2013-10-10
申请号：JP2012081429
申请日：2012-03-30
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： IWAMURO NORIYUKI , HARADA SHINSUKE , HOSHI YASUYUKI , HARADA YUICHI
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To achieve both of improvement in element withstanding voltage and reduction in on-resistance at the same time by generating a depletion layer at a joint surface between a drift layer which is an n-type withstanding voltage region and a high-concentration p-type layer even when an impurity concentration of the drift layer of the silicon carbide vertical MOSFET is increased.SOLUTION: A silicon carbide vertical MOSFET comprises: a first conductivity type well region selectively formed on a surface of a substrate 1; an interlayer insulation film 13 which is formed via a gate insulation film 8 and a gate poly-Si electrode 9, on at least a part of a surface exposed part of a second conductivity type third semiconductor layer 21 sandwiched between a first conductivity type source region 5 and the first conductivity type well region; a source electrode 10 which contacts surfaces of the first conductivity type source region 5 and the third semiconductor layer 21 in common; and a drain electrode 11 formed on a rear face of the silicon carbide substrate 1. At least one layer of high-concentration and second conductivity type semiconductor layers 3, 31 is formed inside the first semiconductor layer 2 on the same position.
摘要翻译：要解决的问题为了同时通过在作为n型耐压区域的漂移层和高压电极之间的接合面处产生耗尽层来实现元件耐受电压的提高和导通电阻的降低，即使当碳化硅垂直MOSFET的漂移层的杂质浓度增加时，浓度p型层也增加。解决方案：碳化硅垂直MOSFET包括：选择性地形成在衬底1的表面上的第一导电类型阱区; 在第二导电类型的第三半导体层21的表面暴露部分的至少一部分上夹着第一导电类型的源极区域和第二导电类型的源极区域之间经由栅极绝缘膜8和栅极多晶硅电极9形成的层间绝缘膜13 5和第一导电类型井区; 与第一导电型源极区域5和第三半导体层21的表面共同接触的源电极10; 以及形成在碳化硅衬底1的背面上的漏电极11.至少一层高浓度和第二导电类型半导体层3,31在第一半导体层2的内部形成在同一位置上。

2. 发明专利

JP2013211460A High-voltage semiconductor device 有权
标题翻译：高断电压半导体器件
公开(公告)号：JP2013211460A
公开(公告)日：2013-10-10
申请号：JP2012081736
申请日：2012-03-30
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： IWAMURO NORIYUKI , HARADA SHINSUKE , HOSHI YASUYUKI , HARADA YUICHI
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/12 , H01L29/47 , H01L29/872
CPC分类号： H01L29/1095 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/0619 , H01L29/0661 , H01L29/0878 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/7811 , H01L29/868 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To improve a breakdown strength with low on-resistance while a sufficient element breakdown voltage characteristic is held for a process variation at the time of ion implantation in a peripheral breakdown voltage structure, independent of crystal plane direction of a substrate.SOLUTION: A vertical high breakdown voltage semiconductor device includes a first conductive type semiconductor substrate (1), a semiconductor layer (2) which is formed on the semiconductor substrate (1) to be first conductivity type and has concentration lower than the semiconductor substrate (1), a second conductivity type semiconductor layer (3) of high concentration which is selectively formed on the surface of the semiconductor layer (2), a base layer (4) of second conductivity type and low concentration, formed on the semiconductor layer (2) and the second conductivity type semiconductor layer (3), and a first conductive type source region (5) which is selectively formed on a surface layer of the base layer (4). At an element peripheral part, a part of the second conductivity type semiconductor layer (3) is removed, and then, on the surface of the semiconductor layer (2) whose concentration is lower than the semiconductor substrate (1), a plurality of second conductivity type layers (11 and 12) of low concentration are formed. The second conductivity type layer (11) at the innermost periphery is arranged not to contact to the second conductivity type semiconductor layer (3) and the base layer (4).
摘要翻译：要解决的问题：为了在外围击穿电压结构中的离子注入时保持足够的元件击穿电压特性，而与基板的晶面方向无关，提高具有低导通电阻的击穿强度。解决方案：垂直高击穿电压半导体器件包括第一导电类型半导体衬底（1），半导体衬底（1）上形成为第一导电类型并具有比半导体衬底低的浓度的半导体层（2） 1），在半导体层（2）的表面上选择性地形成有高浓度的第二导电型半导体层（3），形成在半导体层（2）上的第二导电型和低浓度的基极层（4） 2）和第二导电类型半导体层（3）以及选择性地形成在表面l上的第一导电型源极区域（5）基层（4）。在元件周边部分，去除第二导电类型半导体层（3）的一部分，然后在其半导体层（2）的表面上浓度低于半导体衬底（1）的多个第二形成低浓度的导电型层（11和12）。最外围的第二导电类型层（11）布置成不与第二导电类型半导体层（3）和基底层（4）接触。

3. 发明专利

JP2013232562A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013232562A
公开(公告)日：2013-11-14
申请号：JP2012104230
申请日：2012-04-27
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： IWAMURO NORIYUKI , HOSHI YASUYUKI , HARADA YUICHI , HARADA SHINSUKE
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/1608 , H01L29/0615 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/66068 , H01L29/7395 , H01L29/78 , H01L29/7811 , H01L29/8611 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has an element structure stably exhibiting high voltage withstanding characteristics and which has low on-resistance.SOLUTION: A semiconductor device comprises: an active region 100a including a pregion 3 which is selectively provided on a surface layer of an ndrift layer 2 on an nsemiconductor substrate 1; a p base layer 4 provided on surfaces of the ndrift layer 2 and the pregion 3; a MOS structure provided in the p base layer 4; and a pregion 33 provided on the pregion 3 at a part of the active region 100a where the MOS structure is not formed. The pregion 33 contacts a source electrode 10. The semiconductor device comprises a voltage withstanding structure region 100b in which a JTE structure 13 composed of at least a pregion 21 is provided so as to surround the active region 100a. The JTE structure 13 is provided away from the pregion 3 and the p base layer 4. In addition, the pregion 21 contacts the pregion 33 at a part near a border between the active region 100a and the voltage withstanding structure region 100b where the MOS structure is not formed.
摘要翻译：要解决的问题：提供一种半导体器件，其具有稳定地呈现高耐压特性并且具有低导通电阻的元件结构。半导体器件包括：有源区域100a，其包括选择性地设置在半导体衬底1上的n层层2的表面层; 设置在n层2和前摄体3的表面上的p基层4; 设置在p基层4中的MOS结构; 以及在没有形成MOS结构的有源区域100a的一部分处设置在前摄体3上的前摄体33。前置电极33接触源电极10.半导体器件包括电压承受结构区域100b，其中设置有由至少前导件21构成的JTE结构13，以围绕有源区域100a。 JTE结构13远离前摄体3和p基底层4设置。此外，前置电极21在有源区域100a和耐压结构区域100b之间的边界附近的部分处接触前置电极33，其中MOS结构没有形成。

4. 发明专利

JP2013211440A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013211440A
公开(公告)日：2013-10-10
申请号：JP2012081171
申请日：2012-03-30
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： HARADA YUICHI , IWAMURO NORIYUKI , HOSHI YASUYUKI , HARADA SHINSUKE
IPC分类号： H01L29/78 , H01L29/12
CPC分类号： H01L29/7827 , H01L21/049 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66068 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that improves the dielectric breakdown strength and reliability of an insulating film while maintaining the primary functions as a MOSFET.SOLUTION: A stack in which an N-type SiC layer 2 is formed on a surface of an N-type SiC substrate 1 is used as a basic layer, P-type regions 3 are formed on a surface of the N-type SiC layer 2, and N-type source regions 4 are formed on surfaces of the P-type regions 3. Source electrodes 8 are formed on surfaces of the N-type source regions 4, and a drain electrode 9 is formed on a rear surface side (the other surface side) of the N-type SiC substrate 1. Gate electrodes 7 are formed only on the surfaces of the P-type regions 3 via gate insulating films (oxide films) 6. The configuration eliminates the application of a high voltage between the drain electrode 9 and the gate electrodes 7 due to, such as, the stop of the voltage application to the gate electrodes 7, thereby eliminating the application of a large electric field to the gate insulating films 6.
摘要翻译：要解决的问题：提供一种提高绝缘膜的介电击穿强度和可靠性的半导体器件，同时保持主要功能作为MOSFET。解决方案：在其表面上形成N型SiC层2的堆叠使用N型SiC衬底1作为碱性层，在N型SiC层2的表面上形成有P型区3，在P型区的表面形成有N型源极区4 源极电极8形成在N型源极区域4的表面上，并且在N型SiC衬底1的后表面侧（另一个表面侧）形成漏电极9.形成栅电极7 仅通过栅极绝缘膜（氧化物膜）6在P型区域3的表面上。这种构造消除了由于诸如停止了漏极电极9而导致的漏电极9和栅电极7之间的高电压的施加。施加到栅电极7，从而消除了应用对栅极绝缘膜6的大电场的离子。

5. 发明专利

JP2013232561A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013232561A
公开(公告)日：2013-11-14
申请号：JP2012104229
申请日：2012-04-27
申请人： National Institute Of Advanced Industrial & Technology , 独立行政法人産業技術総合研究所 , Fuji Electric Co Ltd , 富士電機株式会社
发明人： HARADA SHINSUKE , IWAMURO NORIYUKI , HOSHI YASUYUKI , HARADA YUICHI
IPC分类号： H01L29/78 , H01L29/12
CPC分类号： H01L29/1608 , H01L29/0873 , H01L29/0878 , H01L29/36 , H01L29/78 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve insulation breakdown resistance of a gate insulation film and improve reliability of the gate insulation film.SOLUTION: A semiconductor device comprises: an n type SiC layer formed on a surface of an ntype SiC substrate; a plurality of p type regions selectively formed inside the n type SiC layer; a p type SiC layer formed across surfaces of the n type SiC layer and the p type regions; an n type region formed inside the p type SiC layer so as to connect to the n type SiC layer; and an ntype source region and a ptype contact region which are formed inside the p type SiC layer in contact with each other and away from the n type region. The n type region is formed such that a width Lof the n type region inside the p type SiC layer is within a range of 0.8 μm-3.0 μm and an impurity concentration of the n type region is within a range of 1.0×10cm-5.0×10cm. Accordingly, a large electric field is not applied to a gate oxide film thereby to improve breakdown resistance of a gate insulation film and improve reliability of the gate insulation film.
摘要翻译：要解决的问题：提供一种可以提高栅极绝缘膜的绝缘击穿电阻并提高栅极绝缘膜的可靠性的半导体器件。解决方案：一种半导体器件包括：形成在n型SiC表面上的n型SiC层基质; 选择性地形成在n型SiC层内的多个p型区; 形成在n型SiC层和p型区域的表面上的p型SiC层; 形成在p型SiC层内的n型区域，以连接到n型SiC层; 以及形成在p型SiC层内部并且彼此接触并远离n型区域的n型源极区域和p型接触区域。 n型区域形成为使p型SiC层内的n型区域的宽度L在0.8μm〜3.0μm的范围内，n型区域的杂质浓度在1.0×10cm〜5.0的范围内 ×10厘米。因此，不向栅极氧化膜施加大的电场，从而提高栅极绝缘膜的耐击穿性，提高栅极绝缘膜的可靠性。

6. 发明专利

JP2014060426A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014060426A
公开(公告)日：2014-04-03
申请号：JP2013232191
申请日：2013-11-08
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： MATSUI TOSHIYUKI , HOSHI YASUYUKI , KOBAYASHI YASUYUKI , MIYASAKA YASUSHI
IPC分类号： H01L29/861 , H01L21/329 , H01L29/06 , H01L29/868
摘要： PROBLEM TO BE SOLVED: To make a tolerance to an attenuation factor di/dt of reverse recovery current high enough to withstand lightning surge with a forward voltage VF kept low in a converter diode or the like.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: selectively forming pdiffusion regions 23, 24, and 25 having a depth of 14-20 μm (design value) in a surface layer of an nsemiconductor layer 22; and forming a low-lifetime region 32 in a whole chip by irradiating all the chip surface with He ions to introduce a lifetime killer from a position d2 shallower than a position d1 of the plane 31 of PN junction of the nsemiconductor layer 22 and the pdiffusion region 23 to a deep position d3. The irradiation of He ions is performed so that the depth of the pdiffusion region 23 is equal to or larger than a half-value width of the He ion irradiation, a peak position of the He ions is deeper than the half-value width of the He ion irradiation within a range of 80-120% of the depth of the pdiffusion region 23, and the depth of the d1 is deeper than the half-value width of the He ion irradiation.
摘要翻译：要解决的问题：为了使逆向恢复电流的衰减系数di / dt的公差高到足以承受在转换器二极管等中保持较低的正向电压VF的雷电浪涌。解决方案：一种用于制造半导体器件的方法包括以下步骤：在半导体层22的表面层中选择性地形成深度为14-20μm（设计值）的扩散区域23,24和25; 并且通过用He离子照射所有芯片表面，在整个芯片中形成低寿命区域32，以从比半导体层22的PN结的平面31的位置d1更浅的位置d2引入终身杀伤剂，并且扩散区域23到深位置d3。进行He离子的照射，使得扩散区域23的深度等于或大于He离子照射的半值宽度，He离子的峰值位置比其半值宽度更深 He离子辐射在扩散区域23的深度的80-120％的范围内，并且d1的深度比He离子照射的半值宽度更深。

7. 发明专利

JP2017092355A 半導体装置および半導体装置の製造方法审中-公开
公开(公告)号：JP2017092355A
公开(公告)日：2017-05-25
申请号：JP2015223473
申请日：2015-11-13
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： HARADA YUICHI , HOSHI YASUYUKI
IPC分类号： H01L29/78 , H01L29/06 , H01L29/12
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要：【課題】安定して所定の耐圧を確保することができる半導体装置および半導体装置の製造方法を提供すること。【解決手段】炭化珪素基体40のおもて面にエッジ終端領域20を活性領域10よりも低くした段差21が設けられ、段差21の底面21aにn-型炭化珪素層2が露出されている。n-型炭化珪素層2の段差21の底面21aに露出する部分には、JTE構造30を構成する第1,2JTE領域31,32が設けられている。第1JTE領域31は、段差21の底面21aから側壁21bに沿って設けられ、底面コーナー部21cを覆う。第1JTE領域31は、段差21の底面コーナー部21cにおいて最も外側の第1p型ベース領域3に重なっている。第1JTE領域31は、第1p型ベース領域3と重なる部分33で最も高不純物濃度であり、段差21の底面21aよりも深い部分に深さ方向の不純物濃度ピークを有する。【選択図】図1

8. 发明专利

JP2012165013A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012165013A
公开(公告)日：2012-08-30
申请号：JP2012101066
申请日：2012-04-26
申请人： Fuji Electric Co Ltd , 富士電機株式会社
发明人： MATSUI TOSHIYUKI , HOSHI YASUYUKI , KOBAYASHI YASUYUKI , MIYASAKA YASUSHI
IPC分类号： H01L29/868 , H01L21/329 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To sufficiently increase capability of an attenuation factor di/dt of a reverse recovery current to a degree capable of withstanding a lightning surge with keeping a forward voltage VF low in a converter diode and the like.SOLUTION: On a surface layer of an nsemiconductor layer 22, pdiffusion regions 23, 24, 25 of a depth of 14-20 μm (design value) are selectively formed. A He ion is irradiated on the whole of a chip and a lifetime killer is introduced from a position d2 shallower than a position d1 of a PN junction surface 31 including the nsemiconductor layer 22 and the pdiffusion region 23 to a position d3 deeper than the position d1 to form a low lifetime region 32 on the whole of the chip. In irradiation of the He ion, a depth of the pdiffusion region 23 is made to become not shallower than half maximum full-width of irradiation of the He ion, and a peak position of the He ion is made to become deeper than half maximum full-width of irradiation of the He ion and within a range of 80-120% of the depth of the pdiffusion region 23, and a forward voltage VF is made to become 1.2 V or more and 1.5 V or less.
摘要翻译：要解决的问题：为了将逆向恢复电流的衰减系数di / dt的能力充分提高到能够耐受雷电浪涌的程度，并且在转换器二极管等中保持正向电压VF低的能力。解决方案：在n - / SP半导体层22的表面层上，p + 扩散区23,24,25 的深度为14-20μm（设计值）。在整个芯片上照射He离子，并且从比包括n型半导体层的PN结表面31的位置d1更浅的位置d2引入寿命消除器 22和p + 扩散区域23到比位置d1更深的位置d3，以在整个芯片上形成低寿命区域32。在He离子的照射中，使p + 扩散区23的深度不比He离子的照射的半最大全宽更浅，使He离子的位置变得比He离子的照射的半最大全宽更深，并且在p + 的深度的80-120％的范围内扩散区域23，使正向电压VF为1.2V以上且1.5V以下。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2017118139A 半導体装置および半導体装置の製造方法有权
公开(公告)号：JP2017118139A
公开(公告)日：2017-06-29
申请号：JP2017035534
申请日：2017-02-27
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： KINOSHITA AKIMASA , HOSHI YASUYUKI , HARADA YUICHI
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/78 , H01L29/861 , H01L29/868 , H01L29/872
摘要：【課題】高耐圧を維持するとともに、信頼性の高い半導体装置および半導体装置の製造方法を提供すること。【解決手段】p+型ベース領域12は、活性領域101を囲む耐圧構造部102において、内側端部となる。p-型領域3bは、p+型ベース領域12の外周側にp+型ベース領域12に接して設けられ、p+型ベース領域12の周囲を囲む。第1のp-型領域5aは、p-型領域3bの外周側にp-型領域3bと離して設けられ、p-型領域3bの周囲を囲む。第2のp--型領域5bは、第1のp-型領域5aの外周側に第1のp-型領域5aに接して設けられ、第1のp-型領域5aの周囲を囲む。第1のp-型領域5aおよび第2のp--型領域5bは、終端構造を構成する。【選択図】図6

10. 发明专利

JP2017092364A 半導体装置および半導体装置の製造方法审中-公开
公开(公告)号：JP2017092364A
公开(公告)日：2017-05-25
申请号：JP2015223755
申请日：2015-11-16
申请人：富士電機株式会社 , Fuji Electric Co Ltd
发明人： HOSHI YASUYUKI
IPC分类号： H01L29/06 , H01L21/265 , H01L21/336 , H01L29/12 , H01L29/78
摘要：【課題】チップサイズを拡大させることなく、信頼性の高い耐圧構造を備えた半導体装置および半導体装置の製造方法を提供すること。【解決手段】炭化珪素基体40のおもて面にエッジ終端領域20を活性領域10よりも低くした段差21が設けられ、段差21の底面21aにn-型炭化珪素層2が露出されている。n-型炭化珪素層2の段差21の底面21aに露出する部分には、深さ方向にn+型炭化珪素基板1に達しない深さで溝22が選択的に設けられている。第1JTE31は、溝22よりも内側に溝22と離して設けられ、段差21の底面21aにおいて最も外側の第1p型ベース領域3に接する。第2JTE領域32は、溝22の内壁に沿って設けられている。絶縁膜33は、溝22の内部に埋め込まれ、第2JTE領域32に覆われている。第1,2JTE領域31,32のJTE構造30と、溝22の内部に埋め込まれた絶縁膜33とで、耐圧構造が構成される。【選択図】図1

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