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1. 发明专利

JPH11282781A Communication device 失效
标题翻译：通信设备
公开(公告)号：JPH11282781A
公开(公告)日：1999-10-15
申请号：JP8131798
申请日：1998-03-27
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd , 富士通株式会社 , 日本電信電話株式会社 , 沖電気工業株式会社
发明人： KITAMURA TATSUHIKO , WADA SUKEMICHI , KOGURE TAKUYA , ITO ARATA , MURAKAMI TAKAO
IPC分类号： G06F13/14 , G06F13/00
摘要： PROBLEM TO BE SOLVED: To unnecessitate the reset of inherent device data at the time of exchanging device control packages.
SOLUTION: A device control package 10a for controlling this communication device is mounted on a back panel 14 by using a specified connector 12. The device control package has an interface to be connected to a LAN 16. The device control package is equipped with a work station 22 outside and input of data by way of this interface can be performed from the work station. The device control package is equipped with an in-package control part 20 mounting a CPU. The in-package control part controls a sub board 24a as well as the mounted whole device control package. The sub board is connected to the back panel by using a specified connector 26. The sub board and the device control package are connected by the back panel with a signal wiring 28. The sub board is equipped with a storage device 18 where inherent device data such as an IP address are recorded.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：在更换设备控制包时，不必要重置固有的设备数据。解决方案：用于控制该通信设备的设备控制包10a通过使用指定的连接器12安装在后面板14上。设备控制包具有要连接到LAN 16的接口。设备控制包装配有工作站外22，通过该接口输入数据可以从工作站进行。设备控制包装有安装CPU的包装内控制部件20。包装内控制部分控制子板24a以及安装的整个装置控制包装。子板通过使用指定的连接器26连接到后面板。子板和设备控制封装通过背板与信号布线28连接。子板配备有存储装置18，其中固有的装置数据如IP地址被记录。

2. 发明专利

JPH0856228A ATM CELL SWITCH DEVICE AND ATM EXCHANGE 失效
公开(公告)号：JPH0856228A
公开(公告)日：1996-02-27
申请号：JP19034194
申请日：1994-08-12
申请人： OKI ELECTRIC IND CO LTD
发明人： NOIRI AKIRA , MURASUGI MICHIHIRO , WADA SUKEMICHI , KITAMURA TATSUHIKO
IPC分类号： H04Q3/00 , H04L12/70 , H04L12/931 , H04L12/933 , H04L12/951 , H04Q11/04 , H04L12/28 , H04L12/24 , H04L12/26
摘要： PURPOSE:To avoid the concentration of memory write processing and to reduce power supply and signal level fluctuation and superimposition of power noise onto a signal line by providing a simultaneous write control means controlling simultaneous write of received cells to a cell multiplex memory. CONSTITUTION:The exchange is provided with a simultaneous write suppression circuit 252 and a simultaneous write suppression control circuit 253 controlling the circuit 252 to control simultaneous write to a cell multiplex memory 254. The simultaneous write suppression control circuit 253 monitors a timing when input (write) data are arranged and deviates a write timing to the memory 254 so that the number of write requests (write pulses) is uniformed timewise. Since a rapid current change in a cell multiplex section due to memory write is avoided, power supply and signal level fluctuation and superimposition of power noise onto a signal line are reduced.

3. 发明专利

JPH11196003A MULTIPLE CONVERSION METHOD AND DEVICE THEREOF 失效
公开(公告)号：JPH11196003A
公开(公告)日：1999-07-21
申请号：JP35970597
申请日：1997-12-26
申请人： OKI ELECTRIC IND CO LTD
发明人： WADA SUKEMICHI , HAGIO MASAMI
IPC分类号： H03M9/00 , H04J3/00 , H04J3/06
摘要： PROBLEM TO BE SOLVED: To provide a multiple conversion method with which the latch timing is not limited by an input frame signal by setting set of delay data to be used for the multiple conversion among those delay data strings which have been prepared in number which is equivalent to the number of stages corresponding to a reference conversion cycle and then latching the set of data in the prescribed latch timing, that is decided regardless of the input frame signal. SOLUTION: A shift register stage 1 successively delays input data and outputs delay data strings which are equivalent to the number of stages corresponding to a reference conversion cycle, that is decided based on the relation between the bit width of the input data and that of the output data. An input frame phase decision means 2 decides the specific phase of the reference conversion cycle in which the input frame signal showing the head position of the input data is located. Then the means 2 sets a set of delay data from among delay data strings to be used it for the multiple conversion. An output data output means 3 latches the set of delay data in a prescribed latch timing that has been decided, irrespective of the input frame signal and then outputs this latching result.

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