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1. 发明专利

JPS58137351A BACKUP POWER SOURCE DETECTING CIRCUIT 失效
公开(公告)号：JPS58137351A
公开(公告)日：1983-08-15
申请号：JP2004482
申请日：1982-02-10
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SANO YOSHIO , FUKAZAWA HIDEO , YOSHITOSHI MAKOTO , NISHINO YUTAKA
IPC分类号： H04M1/27 , H04M1/272 , H04M1/2745
摘要： PURPOSE:To prevent erroneous redialing, by detecting a backup power supply voltage, and inhibiting redialing operation when the detected voltage is less than a specific value. CONSTITUTION:When the charging voltage of a backup power source BUP is greater than a specific value, the output of a gate circuit G is at a low level and a transistor (TR) Q3 turns off. Therefore, when a dial key KRD is turned on after off-hook operation, a redialing signal RD is outputted from a TRQ2. On the other hand, when the voltage of the power source BUP is less than the specific value, the output of the gate circuit G is at a high level and the TRQ3 turns on. In this case, the TRQ2 is still off even when the key KRD is turned on, so no redialing signal RD is outputted. Further, the light emission of a light emitting diode LED is maintained to provide visible display for showing whether redialing is possible or not when the key KRD is turned on.

2. 发明专利

JPH0546158B2 失效
公开(公告)号：JPH0546158B2
公开(公告)日：1993-07-13
申请号：JP18418183
申请日：1983-09-30
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FUKAZAWA HIDEO , SANO TAKAMICHI , INOE YOSHIAKI , NAGAI NAOFUMI , SHIMOHARA KATSUNORI , MATSUO NAOKI
IPC分类号： H02J9/06 , H04M19/00 , H04Q1/28
摘要： PURPOSE:To decrease power feeding from a spare power supply by blocking calling at commercial power failure in a private branch of exchange driven by the commercial power supply and the spare power supply. CONSTITUTION:The power supply POW supplies a prescribed power by using a commercial power source AC and rectifier circuits PW1, PW2 and charges up batteries B1, B2 as the spare power supply by means by floating. When the power source AC is failed, power failure is informed to a processor by a power failure detecting circuit PD, the processor supervises the idle/busy state of extensions EXT1-n, brings a signal line PEi corresponding to an extension of idle state to a high potential, blocks power feeding and blocks calling. Moreover, the power supply fed to the processor is interrupted except for a storage circuit RAM. When the power failure is restored and the power of the commercial power source AC is restored, the power failure detecting circuit PD stops the information of power falure to the processor and the rectifier circuits PW1, PW2 supply again the prescribed power.

3. 发明专利

JPS6075197A DIGITAL TELEPHONE TERMINAL INTERFACE CIRCUIT 失效
公开(公告)号：JPS6075197A
公开(公告)日：1985-04-27
申请号：JP18417983
申请日：1983-09-30
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SANO YOSHIO , FUKAZAWA HIDEO , NAGAI NAOFUMI , SHIMOHARA KATSUNORI
IPC分类号： H04Q3/42 , H04J3/06 , H04M1/00 , H04M1/253 , H04Q3/58 , H04Q11/04
摘要： PURPOSE:To consitute identically a line terminating device with an interface circuit of a digial telephone set by switching and generating a clock signal of the interface circuit in synchronizing with a clock signal incoming externally. CONSTITUTION:When the interface circuit 5' is used as the line terminating device, a standard clock signal of 8kHz is fed from a standard clock source to a terminal 57, and a signal allowing a selecting circuit 504 to select the standard clock signal of 8kHz is inputted to a terminal 59. As a result, all the clock signals are synchronized with the clock signal of 8kHz. On the other hand, when the circuit 5' is used for a digital telephone terminal device, a signal allowing the selection circuit 504 to select a reception signal of 80k-bit/sec is inputted to the terminal 59, resulting that a clock forming signal circit 506 outputs the clock signals of 64kHz and 8kHz synchronized with the reception signal of 80k bit/sec to terminals 57', 58' so as to use it as a reference of the clock signal applied from the circuit 507.

4. 发明专利

JPS5694895A CONFERENCEETYPE COMMUNICATION PROCESS SYSTEM 失效
公开(公告)号：JPS5694895A
公开(公告)日：1981-07-31
申请号：JP17368379
申请日：1979-12-27
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SATOU HIROAKI , FUKAZAWA HIDEO , NAKANO YOSHIO , NAGAI NAOFUMI
IPC分类号： H04M3/56 , H04M9/02 , H04Q11/04
摘要： PURPOSE:To realize a conference-type call for three persons or more via the single channel in a frame, by providing an attenuator at the single channel in the frame information and adding a data compounding part to each channel to add the own- generated information to the information given from other channels. CONSTITUTION:The loop transmission units 2-0-2-3 are connected by the loop transmission lines 3-0, and the attenuator LOSS is provided to the unit 2-0 which functions as the master station. At the same time, the data compounding parts 11-1-11-3 plus 12-1-12-3 are added to the units 2-1-2-3 to add the information of the own transmitter microphones 9-1-9-3 to the other information of other channels. Furthermore, the compound data receiving parts 12-1-12-3 are connected to the telephone receivers 10-1-10-3. Then the transmission of the frame information are given to N channels, and the data of the N channels can be attenuated by the attenuator LOSS. Thus a conference-type call becomes possible for three persons or more with use of the single channel in the frame.

5. 发明专利

JPS60260242A HIGHWAY MULTIPLEX SYSTEM 失效
公开(公告)号：JPS60260242A
公开(公告)日：1985-12-23
申请号：JP11605084
申请日：1984-06-06
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SHIMOE TOSHIO , FUKAZAWA HIDEO , NISHIMURA MASAYUKI , NOMURA MASAYUKI , DOI EIJI
IPC分类号： H04J3/06
摘要： PURPOSE:To simplify a flag pattern detecting means by adding a violation VL different from a VL added to a frame synchronizing pattern to a flag pattern identifying a group of information to a channel and transmitting the result. CONSTITUTION:In constituting a frame through the time division of plural channels and transmitting the frame, a direct memory access control circuit 17 applies P/S conversion 19 to the information from a memory 15 via a buffer 18 by a command of a microprocessor 14 and transmits the result to a selection circuit 22. A timing circuit 16 starts a flag pattern generating circuit 21', allows the circuit 21' to generate a code of a flag pattern FL' and transmits the result to the circuit 22. The circuit 22 selects the code FL' and the information from the circuit 19 to constitute a packet and the result is fed to a multiplex circuit 23. Further, a frame FR synchronizing pattern generating circuit 24 transmits an FR synchronizing pattern F to the circuit 23, then the circuit 23 multiplexes the pattern F and the packet and transmits the result to a VL set code converting circuit 25'. The circuit 25' adds a VL to the pattern F and adds a different VL to the pattern FL' and transmits the result to a highway 27.

6. 发明专利

JPS58123265A PUSH-BUTTON DIAL TELEPHONE SET 失效
公开(公告)号：JPS58123265A
公开(公告)日：1983-07-22
申请号：JP557882
申请日：1982-01-18
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： FUKAZAWA HIDEO , ARAI MASATAKA , NISHINO YUTAKA , NISHIMURA SHINJI
IPC分类号： H04M1/27 , H04M1/50
摘要： PURPOSE:To select the combination of one wave of a low and a high group and to prevent erroneous key input, by providing a key interface with a function for inhibiting the transmission of a multifrequency signal only during one period wherein the power source of a multifrequency signal generation part is turned on and its oscillation state attains stable. CONSTITUTION:The key interface circuit KIF is provided with a key input part KEY and the multifrequency signal generation part MFSG. To this circuit KIF, the multifrequency signal generation part MFSG is connected and the mixer MIX of the circuit mixes one output wave of a programmable counter PCTRH for low-group frequency generation with that of a programmable counter PCTR1 for high-group frequency generation to apply the resulting signal to a receiving amplifier TAMP connected to a handset T. The output of this amplifier TAMP is connected to a hybrid circuit HYB connected to the circuit KIF. For a specific time from the power-up operation of the circuit MFSG to the oscillation stabilization of the oscillator OSC, the transmission of a multifrequency signal is inhibited to prevent erroneous key input.

7. 发明专利

JPS58108856A SIGNAL SEPARATION CONTROL SYSTEM OF TERMINAL CONTROLLER 失效
公开(公告)号：JPS58108856A
公开(公告)日：1983-06-29
申请号：JP20876881
申请日：1981-12-22
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： INOUE YOSHIAKI , FUKAZAWA HIDEO , HAMADA MICHIHIRO , NAGAI NAOFUMI , SHIMOHARA KATSUNORI
IPC分类号： H04M11/00 , H04M11/06 , H04M19/00
摘要： PURPOSE:To prevent a fault from occurring to the circuit part of an office feeding system by providing a means of separating a signal in case of a power failure between the circuit part of the office feeding system and the circuit part of an AC feeding system. CONSTITUTION:A signal separation part 2 is provided between the circuit part 1 of the office feeding system and the circuit part 3 of the AC feeding system, and this separation part 2 consists of tristate gate circuits A1, A2 and B1; a circuit part in a power failure state is opened and the other normal circuit part is held at a low level ''0'' or high level ''1''. Therefore, signal separation between the circuit parts 1 and 3 prevents the occurrence of a fault at the circuit part in the power failure state and also prevents the malfunction of the other normal circuit part. Those tristate gate circuits cab be integrated and even when the number of signals lines to be separated by the signal separation part 2 is large, the whole of the signal separation part 2 can be IC-implemented.

8. 发明专利

JPS57190448A CALLING CIRCUIT FOR TELEPHONE 失效
公开(公告)号：JPS57190448A
公开(公告)日：1982-11-24
申请号：JP7492381
申请日：1981-05-20
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TOKUDA MASAMI , FUKAZAWA HIDEO , NISHIMURA SHINJI , NISHINO YUTAKA
IPC分类号： H04M1/00 , H04M19/04
摘要： PURPOSE:To remove an uncomfortable sound component from a telephone ringing tone by stopping the generation of the ringing tone based upon the detection of the end of a square wave signal. CONSTITUTION:An input from an input terminal 1 is rectified and applied to a square wave signal generating circuit 3 and a counter 5 starts time counting from the rise time of a square wave signal of 16Hz, the output of the circuit 3. When the succeeding square wave pulse arrives after passing 60ms e.g. from the rise time, an output signal from the counter 5 to a gate 6 is still ''1'', but said output signal is turned to ''0'' in case of no arrival. When the output signal is turned to ''0'', an output signal from an audible signal generating circuit 4 to the gate 6 is checked and the operation of a sounder driving circuit 1 is stopped. Thus, an uncomfortable sound to be generated in accordance with the drop of an output rectifying voltage waveform at the suspending time of the ringing tone applied between input terminals P1, P2 is checked.

9. 发明专利

JPS533106A TELEPHON SET OSCILLATOR 失效
公开(公告)号：JPS533106A
公开(公告)日：1978-01-12
申请号：JP7652376
申请日：1976-06-30
申请人： IWATSU ELECTRIC CO LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , TOKYO SHIBAURA ELECTRIC CO , NIPPON ELECTRIC CO , HITACHI LTD , FUJITSU LTD
发明人： YAMAGISHI FUJIO , UENO KATSUTO , NAKAZAWA HAJIME , TAJIYOU TADASHI , IYOSUMI KENICHI , YOKOO TOSHIO , HIRAKAWA MAKOTO , FUKAZAWA HIDEO
IPC分类号： H03B5/12 , H04M1/50
摘要： PURPOSE:To delete the capacity occurring between windings of the coil used for a resonance circuit and thus to increase the production efficiency of the coil for the telephone set which transmits a multi-frequency aural wave signal.

10. 发明专利

JPS61203746A SYNCHRONOUS SYSTEM FOR SUBSCRIBER'S TRANSMISSION SYSTEM 失效
公开(公告)号：JPS61203746A
公开(公告)日：1986-09-09
申请号：JP4547685
申请日：1985-03-07
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SANO YOSHIO , FUKAZAWA HIDEO , KUBO TERUYUKI , NODA NOBUHIRO
IPC分类号： H04J3/06 , H04L7/02 , H04L7/027 , H04M5/20
摘要： PURPOSE:To simplify the device constitution by sending a reference signal to a bus while being multiplexed in response to a load signal and using a clock of the synchronized reference signal to separate and receive an input multiplexing signal. CONSTITUTION:A reference signal is differentiated by using a clock E or 2E of a subscriber's controller 12 at the subscriber's controller side to generate a load signal, which is sent to a bus transmission line 17. A receiver 21 receives a signal of the line 17 in extension adaptors 191-193 for INS to generate reference signal clocks CK2-CK5 synchronized therewith and a control circuit 24 separates the signals into digital signals corresponding to extensions 181-183 for INS and an INS interface circuit 26 applies the separated signals to the extensions 181-183. On the other hand, the signals from the extensions 181-183 for INS are converted into a signals for the bus at a driver 24, sent to the line 17 and then sent to a trunk line.

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