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    • 1. 发明专利
    • SYSTEM FAULT ANALYZING SYSTEM
    • JPS56105544A
    • 1981-08-22
    • JP858480
    • 1980-01-28
    • NIPPON ELECTRIC CONIPPON TELEGRAPH & TELEPHONE
    • HOSOKAWA YASUJIARAI KAZUAKITSUGAWA KINGOHARA KENJI
    • G06F11/22
    • PURPOSE:To make the detection of faults easy by storing the logic addresses and physical addresses of a random-accessible memory means in pairs into an address conversion means and reading out the storage contents assigned by the physical addresses. CONSTITUTION:The contents of a magnetic tape 1 having recorded all of memory information are transferred by a transfer mechanism 6 to a magnetic disc 7. At this time, the physical addresses of the disc 7 and the physical address information at the making of the tape 1 are stored in pairs from the mechanism 6 into a mapping mechanism 8. The top address and state information of the 1st block have beforehand been stored in a random address mechanism 9, and the logic addresses are applied from the mechanism 9 to the mechanism 8. The corresponding physical addresses are applied to the disc 7. The contents of the positions assigned by the physical addresses are applied to the mechanism 9, and these pieces of information of the mechanism 9 are applied in a set to a control block reproducing mechanism 10. The mechanism 10 edits such information in an easy-to-fault-analyze manner, after which said information is printed with a printer 2.