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1. 发明专利

JP2010040667A Method for manufacturing semiconductor device, and device for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法和用于制造半导体器件的器件
公开(公告)号：JP2010040667A
公开(公告)日：2010-02-18
申请号：JP2008199977
申请日：2008-08-01
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA
IPC分类号： H01L21/288 , C25D7/12 , C25D21/14
摘要： PROBLEM TO BE SOLVED: To maintain the quality of plating processing by computing concentrations of components contained in a plating liquid and suitably adjusting the plating liquid.
SOLUTION: A method for manufacturing a semiconductor device includes: a step of adding one or a plurality of additives to the plating liquid and performing plating processing on a semiconductor wafer (step S1); a step of measuring one or a plurality of parameters showing the processing state of the plating processing (step S3); a step of computing the concentrations of components contained in the plating liquid from the parameters (step S4); and a step of performing adjustment processing on the plating liquid, so that the computed concentrations of the components are equal to or less than predetermined thresholds (step S6).
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过计算包含在电镀液中的组分的浓度并适当地调节电镀液体来保持电镀处理的质量。解决方案：一种制造半导体器件的方法包括：向电镀液中添加一种或多种添加剂并对半导体晶片进行电镀处理的步骤（步骤S1）; 测量表示电镀处理的处理状态的一个或多个参数的步骤（步骤S3）; 从参数计算包含在电镀液中的成分的浓度的步骤（步骤S4）; 以及对电镀液进行调整处理的步骤，使得计算出的成分浓度等于或小于预定阈值（步骤S6）。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009191295A Method for manufacturing semiconductor device, and plating apparatus 有权
标题翻译：制造半导体器件的方法和镀膜装置
公开(公告)号：JP2009191295A
公开(公告)日：2009-08-27
申请号：JP2008030875
申请日：2008-02-12
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA
IPC分类号： C25D21/12 , C25D7/12 , H01L21/288
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device by which the occurrence of an error between the surface potential of a surface to be plated, and a desired surface potential can be suppressed in spite of progression of deposition of a plating film.
SOLUTION: The method for manufacturing the semiconductor device includes: a step of bringing a sheet film 20 formed on a semiconductor substrate 1 into contact with a plating solution 32; and a step of connecting a cathode electrode 54 to the sheet film 20 and forming a plating film 22 on the sheet film 20 by allowing an electric current to flow between the sheet film 20 and an anode electrode 40. In the step of forming the plating film 20, the method includes a step of gradually lowering the potential difference between a reference electrode 34 inserted into the plating solution 20 and the cathode electrode 54, or between the cathode electrode 54 and an anode electrode 40.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于制造半导体器件的方法，通过该方法可以抑制待镀表面的表面电位和期望的表面电位之间的误差的发生，尽管沉积的进行镀膜。解决方案：制造半导体器件的方法包括：使形成在半导体衬底1上的片状膜20与电镀液32接触的步骤; 以及通过允许电流在片状膜20和阳极电极40之间流动而将阴极电极54连接到片状膜20并在片状膜20上形成镀膜22的步骤。在形成电镀的步骤膜20，该方法包括逐渐降低插入到电镀液20中的参考电极34与阴极电极54之间或者阴极电极54与阳极电极40之间的电位差的步骤。版权所有（C））2009，JPO＆INPIT

3. 发明专利

JP2008283124A Method of manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2008283124A
公开(公告)日：2008-11-20
申请号：JP2007128108
申请日：2007-05-14
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA
IPC分类号： H01L21/3205 , C25D5/18 , C25D7/12 , C25D21/12 , H01L21/288
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a reliable semiconductor device, where the number of defects in a plating film after a CMP process is reduced. SOLUTION: The manufacturing method includes: a process for forming a seed film on a substrate including a recess on which a fine pattern is formed and a recess formed wider than the fine pattern; and an electrolytic plating process for burying the recesses with a plating liquid containing an accelerator and a retarder. The electrolytic plating process includes: a first electrolytic plating process for burying the recess on which a fine pattern is formed with first current density; a first reverse bias process for energizing current having a polarity differing from that in the electrolytic plating process with second current density; a process for performing second electrolytic plating with third current density larger than the first current density; a second reverse bias process for performing energization with fourth current density; and a process for performing third electrolytic plating with fifth current density larger than the first current density. An absolute value of an integrated quantity of current in the second reverse bias process is larger than that of an integrated quantity of current in the first one. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造可靠的半导体器件的方法，其中CMP工艺之后的镀膜中的缺陷数量减少。解决方案：制造方法包括：在包括形成微细图案的凹部和形成为比精细图案更宽的凹部的基板上形成种子膜的工艺; 以及用于将包含加速器和延迟器的镀液埋入凹部的电解电镀工艺。电解电镀工艺包括：第一电解电镀工艺，用于以第一电流密度掩埋形成精细图案的凹槽; 用于对具有与电解电镀工艺中的极性不同的极性的电流进行第二电流密度的第一反向偏压工艺; 用于进行第三电流密度大于第一电流密度的第二电镀的工艺; 用于以第四电流密度进行通电的第二反向偏置工艺; 以及进行具有比第一电流密度大的第五电流密度的第三电解电镀的工序。第二反向偏置处理中的积分电流的绝对值大于第一反向偏置处理中的积分电流量的绝对值。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008283123A Method of manufacturing semiconductor device, and semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2008283123A
公开(公告)日：2008-11-20
申请号：JP2007128106
申请日：2007-05-14
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA , KOSUMI SHINSUKE , ARITA KOJI
IPC分类号： H01L21/3205 , C25D5/18 , C25D7/12 , H01L21/288
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a reliable semiconductor device, where the number of defects in a plating film after a CMP process is reduced. SOLUTION: The manufacturing method includes: a process for forming a seed film on a substrate including a recess on which a fine pattern is formed and a recess formed wider than the fine pattern; and an electrolytic plating process for burying the recesses with a plating liquid containing an accelerator and a retarder with the seed film as a cathode. The electrolytic plating process includes: a first electrolytic plating process for burying the recess on which a fine pattern is formed with first current density by electrolytic plating; a first reverse bias process for energizing current having a polarity differing from that in the first electrolytic plating process with second current density; a process for performing second electrolytic plating with third current density larger than the first current density; a second reverse bias process for performing energization with fourth current density; and a process for performing third electrolytic plating with fifth current density larger than the first current density. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造可靠的半导体器件的方法，其中CMP工艺之后的镀膜中的缺陷数量减少。解决方案：制造方法包括：在包括形成微细图案的凹部和形成为比精细图案更宽的凹部的基板上形成种子膜的工艺; 以及电解电镀工艺，用含有促进剂和延迟剂的电镀液将该凹陷埋入种子膜作为阴极。电解电镀工艺包括：通过电解电镀将第一电流密度埋在其上形成精细图案的凹部的第一电解电镀工艺; 第一反向偏压工艺，用于对具有与第一电解电镀工艺中的极性不同的极性的电流进行通电，具有第二电流密度; 用于进行第三电流密度大于第一电流密度的第二电镀的工艺; 用于以第四电流密度进行通电的第二反向偏置工艺; 以及进行具有比第一电流密度大的第五电流密度的第三电解电镀的工序。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008141088A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008141088A
公开(公告)日：2008-06-19
申请号：JP2006327866
申请日：2006-12-05
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA
IPC分类号： H01L21/288 , C25D7/12 , C25D21/12 , H01L21/3205
CPC分类号： H01L21/76877 , H01L21/2885
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing semiconductor device which forms a copper film excellent in electrical properties by a simple configuration.
SOLUTION: The method for manufacturing semiconductor device includes: a step S10 for forming a barrier metal film on a semiconductor substrate, where the barrier metal film becomes a seed film acting as a cathode when a copper film is formed by an electrolytic plating method; a step S20 for immersing the barrier metal film in a copper sulfate plating liquid stored in a plating tub for a predetermined period with the barrier metal film and an anode kept at nearly the same potential; and a step S30 for forming the copper film on the surface of the barrier metal film by applying a voltage between the barrier metal film and the anode as it is that the barrier metal film is immersed in the plating liquid, after the barrier metal film is immersed in the copper sulfate plating liquid for the predetermined period.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种通过简单的结构形成电性能优异的铜膜的半导体器件的制造方法。解决方案：半导体器件的制造方法包括：步骤S10，用于在半导体衬底上形成阻挡金属膜，其中当通过电解电镀形成铜膜时，阻挡金属膜变为用作阴极的种子膜方法; 将阻挡金属膜浸渍在电镀槽中储存的硫酸铜电镀液中一段规定时间的步骤S20，其中阻挡金属膜和阳极保持在几乎相同的电位; 以及步骤S30，通过在阻挡金属膜和阳极之间施加电压使阻挡金属膜浸入电镀液中，在阻挡金属膜的表面上形成铜膜，在阻挡金属膜为在硫酸铜电镀液中浸渍规定时间。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2006322070A PLATING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME AND PLATING APPARATUS 审中-公开
公开(公告)号：JP2006322070A
公开(公告)日：2006-11-30
申请号：JP2006116933
申请日：2006-04-20
申请人： NEC ELECTRONICS CORP
发明人： FURUYA AKIRA , TSUCHIYA YASUAKI
IPC分类号： C25D21/12 , C25D7/12 , C25D17/00 , C25D17/06
摘要： PROBLEM TO BE SOLVED: To provide a plating method by which a conductive film is formed through an electroplating method, a method for manufacturing a semiconductor device using the same, and a plating apparatus for stably forming a plating film. SOLUTION: In the plating method, steps 101 and 103 are successively performed. In step 101, a film formation target surface of a wafer 109 is connected to a cathode electrode 107 and inclined relative to a liquid level of a plating solution 103, and the wafer 109 is immersed into a plating solution 103 while first electric current is applied to the cathode electrode 107 and an anode electrode 105 placed in the plating solution 103. In step 103, after the film formation target surface is immersed into the plating solution 103, second electric current is applied to the cathode electrode 107 and the Cu anode electrode 105, and a metal film is grown on the film formation target surface through the electroplating method. In step 101, the first electric current is regulated based on the angle of inclination of the film formation target surface relative to the liquid level. COPYRIGHT: (C)2007,JPO&INPIT

7. 发明专利

JP2006156614A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006156614A
公开(公告)日：2006-06-15
申请号：JP2004343443
申请日：2004-11-29
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA , OTSUKA NOBUYUKI , OKAMURA HIROSHI , OGAWA SHINICHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/336 , H01L29/78
CPC分类号： H01L21/76846 , H01L21/318 , H01L21/3185 , H01L21/76855 , H01L21/76862 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is provided with a barrier metal having high adhesiveness and diffusion preventive property, and also to provide its manufacturing method. SOLUTION: The method for manufacturing a semiconductor device includes steps of: forming a first layer made of a material containing silicon on a substrate; forming a second layer containing metal and nitrogen on the first layer; and exposing the second layer to active species that is obtained from atmospheric plasma containing a reducing gas. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有高粘合性和扩散防止性的阻挡金属的半导体器件，并且还提供其制造方法。解决方案：半导体器件的制造方法包括以下步骤：在基板上形成由含有硅的材料制成的第一层; 在所述第一层上形成含有金属和氮的第二层; 并将第二层暴露于由含有还原气体的大气等离子体获得的活性物质。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005229093A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005229093A
公开(公告)日：2005-08-25
申请号：JP2004327615
申请日：2004-11-11
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA , SODA EIICHI , OGAWA SHINICHI
IPC分类号： H01L21/3065 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device or a method for manufacturing the semiconductor device for preventing diffusion to the interlayer insulating film of a wiring material, such as a barrier metal and Cu.
SOLUTION: The method has a porous insulating film forming process (S104) for forming the porous insulating film 30 on a substrate 10; an SiOC insulating film forming process (S108) for forming an SiOC insulating film 70 on the porous insulating film 30; an aperture forming process (S110-S114) for exposing the porous insulating film 30 and the SiOC insulating film 70 to the atmosphere of plasma of mixed gas of CF
4 , N
2 and Ar, and for forming an aperture 50 continuing to the porous insulating film 30 and the SiOC insulating film 70; and a conductive material deposition process (S116-S120) for depositing the barrier metal film 80 and Cu to the aperture 50.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供半导体器件或半导体器件的制造方法，用于防止扩散到诸如阻挡金属和Cu的布线材料的层间绝缘膜。解决方案：该方法具有用于在基板10上形成多孔绝缘膜30的多孔绝缘膜形成工艺（S104）在多孔绝缘膜30上形成SiOC绝缘膜70的SiOC绝缘膜形成工序（S108）用于将多孔绝缘膜30和SiOC绝缘膜70暴露于CF 4 ，N 2 的混合气体的等离子体气氛的孔形成工艺（S110-S114）和Ar，并且用于形成连续到多孔绝缘膜30和SiOC绝缘膜70的孔50; 以及用于将阻挡金属膜80和Cu沉积到孔50的导电材料沉积工艺（S116-S120）。（C）2005，JPO和NCIPI

9. 发明专利

JP2009289828A Manufacturing method of semiconductor device, and semiconductor device 有权
标题翻译：半导体器件的制造方法和半导体器件
公开(公告)号：JP2009289828A
公开(公告)日：2009-12-10
申请号：JP2008138490
申请日：2008-05-27
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA , KAKITA SHINICHIRO , KUDO MASAMICHI
IPC分类号： H01L21/288 , C25D5/10 , C25D7/12 , H01L21/3205 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To keep film quality of a plated film in fat wiring good while keeping flatness of the plated film.
SOLUTION: This manufacturing method of a semiconductor device includes a first plated film growth step (S102) of embedding thin wiring by a plated film and a second plated film growth step (S108) of embedding fat wiring by the plated film, when embedding a thin recessed part and a fat recessed part by the plate film; when executing a process (S104) of removing an additive in a reverse bias step of facilitating flattening after S102, a slow step (S106) of growing the plated film on the thin recessed part and the fat recessed part by carrying a current of a low current value relative to that in the second plated film growth step in the same direction as that of the first plated film growth step, is inserted after the reverse bias step and before the second plated film growth step.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了保持电镀膜的电泳质量良好，同时保持镀膜的平坦度。解决方案：这种半导体器件的制造方法包括通过镀膜包埋薄布线的第一镀膜生长步骤（S102）和通过镀膜包埋脂肪布线的第二镀膜生长步骤（S108），当通过板膜嵌入薄的凹部和脂肪凹部; 当执行在S102之后的有助于平坦化的反向偏压步骤中去除添加剂的处理（S104）时，通过承载低电流的薄的凹部和脂肪凹部生长电镀膜的缓慢的步骤（S106）在与第一镀膜生长步骤相同的方向上的电流值相对于第二镀膜生长步骤中的电流值插入反向偏压步骤之后并在第二镀膜生长步骤之前。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2007103546A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007103546A
公开(公告)日：2007-04-19
申请号：JP2005289574
申请日：2005-10-03
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： FURUYA AKIRA
IPC分类号： H01L21/3205 , H01L23/52
CPC分类号： H01L21/76849 , H01L21/76822 , H01L21/76834 , H01L21/76867 , H01L21/76886 , H01L21/76888
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can enhance the reliability of copper wiring.
SOLUTION: A semiconductor device 100 comprises a lower layer, a semiconductor substrate 150, an insulation film 102 formed on the semiconductor substrate 150, a wiring metal film 106 containing copper as a main ingredient provided by embedding a recess formed on the surface of the lower layer insulation film 102, an upper insulation film 110 formed on the lower layer insulation film 102, and a metal inclusion layer 108 containing metal different from copper formed between the lower layer insulation film 102 and the upper insulation film 110. The metal inclusion layer 108 includes a first region 108a brought into contact with the wiring metal film 106, and a second region 108b that differs in the composition of the first region 108a while being brought into contact with the lower layer insulation film 102 without containing nitrogen substantially in the first region 108a at least.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可以提高铜布线的可靠性的半导体器件及其制造方法。解决方案：半导体器件100包括下层，半导体衬底150，形成在半导体衬底150上的绝缘膜102，以铜为主要成分的布线金属膜106，其通过嵌入在表面上形成的凹部的下层绝缘膜102，形成在下层绝缘膜102上的上部绝缘膜110和在下层绝缘膜102和上部绝缘膜110之间形成有不同于铜的金属的金属夹杂层108.金属夹杂层108包括与布线金属膜106接触的第一区域108a和第二区域108b，第二区域108b在与第一区域108a的组成不同的同时与下层绝缘膜102接触而不含氮，第一区域108a至少。版权所有（C）2007，JPO＆INPIT

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