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1. 发明专利

JPH05191408A ALARM PROCESSING CIRCUIT 失效
公开(公告)号：JPH05191408A
公开(公告)日：1993-07-30
申请号：JP2044292
申请日：1992-01-08
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , HITACHI LTD
发明人： IKEMATSU RYUICHI , MIYAMOTO AKIHIRO , KANAYAMA YUKIHARU , UEDA HIROMI , TANIGUCHI MITSUKI , TEZUKA KOJI , ASHI MASAHIRO , NAKANO YUKIO
IPC分类号： H04L12/70 , H04B17/00 , H04L12/24 , H04L12/26 , H04L12/28 , H04Q11/04
摘要： PURPOSE:To realize an alarm processing circuit suitable for ATM communication. CONSTITUTION:The circuit is provided with a cell type discrimination circuit 2 discriminating a cell type in response to information in an ATM cell and with a state management table 4 using virtual path specific information in the ATM cell as a detection address and storing the state of each virtual path and also with a detection release processing section 3 being a means which detects a fault based on the cell type by the cell type discrimination circuit 2 and on the state information in the table 4 retrieved by the virtual path specific information and rewrites the content of the state management table 4 corresponding to the virtual path. Thus, valid alarm processing to each virtual path is implemented.

2. 发明专利

JPH05244187A 失效
公开(公告)号：JPH05244187A
公开(公告)日：1993-09-21
申请号：JP2837292
申请日：1992-02-14
申请人： NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD , FUJITSU LTD
发明人： UEDA HIROMI , AKUTSU KENJI , IKEMATSU RYUICHI , KURANO TAKANORI , ASHI MASAHIRO , NAKANO YUKIO , NAKAJO TAKAFUMI , AMAMIYA SHIGEO
IPC分类号： H04L12/70 , H04Q11/04 , H04L12/48
摘要： PURPOSE:To make a cyclic monitoring without deteriorating the throughput by monitoring cyclic cells generated with the use of the unrequired SDH overhead area from the SDH terminal. CONSTITUTION:A signal terminated in a SDH terminal section 31 is converted from an intra-device frame 11 into an intra-device frame 12 in a cyclic cell generation section 32. In short, removing the SOH and POH of the intra-device frame 11, and the cyclic cell generated in the constant cycle is inserted into the section. The cycle of generating the cyclic cell is an intra-device frame phase, and in this case, it represents the insertion in the STM-N two-frame cycle. Further, a monitoring pattern insertion section 33 detects the cyclic cell from the intra-device frame phase and the monitoring pattern written in the cyclic cell is collated by a monitoring pattern collation section 34 to make an intra-device monitoring. Then a STM constitution section 35 establishes the STM-N frame after abolishing the cyclic cell.

3. 发明专利

JPH05292118A 失效
公开(公告)号：JPH05292118A
公开(公告)日：1993-11-05
申请号：JP9468292
申请日：1992-04-15
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD
发明人： TANIGUCHI IKUO , HANAOKA SUSUMU , OTA HIROSHI , UEDA HIROMI , KURANO TAKANORI , NISHIHARA MOTOO , ASHI MASAHIRO , NAKANO YUKIO
IPC分类号： H03M13/00 , H04L12/24 , H04L12/26 , H04L12/48
摘要： PURPOSE:To reduce the scale of the circuit and to decrease a delay in a line with respect to the transmission quality supervisory system in the transmitter/ receiver and communication system for the communication employing the ATM system. CONSTITUTION:A transmitter 310 is configured such that when a user cell number reaches a required number and an idle cell detection section 220 detects an idle cell, an output section 105 inserts the result from the calculation for error supervision for each transmission path (VP) at a transmission arithmetic operation section 100 to an idle cell based on a control signal outputted from a cell number variable control section 250 and sends the result as a supervisory OAM cell. Furthermore, a receiver 320 uses an error discrimination section 200 to compare the result obtained by the arithmetic operation for error supervision as to a block separated by an OAM cell received by a reception arithmetic operation section 110 with the result of arithmetic operation extracted from the OAM cell received by a reception information extract section 180 thereby implementing error supervision to a cell string of variable length.

4. 发明专利

JPH05252188A 失效
公开(公告)号：JPH05252188A
公开(公告)日：1993-09-28
申请号：JP5005692
申请日：1992-03-06
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD , NEC CORP
发明人： ASHI MASAHIRO , TAKATORI MASAHIRO , NAKANO YUKIO , TAKASE MASAHIKO , UEDA HIROMI , NAKAJIMA TAKASHI , TAKEO HIROSHI , KAWAI MASAAKI , TANIGUCHI IKUO , KURANO TAKANORI , NISHIHARA MOTOO
IPC分类号： H04L7/00 , H04L12/28 , H04L12/48
摘要： PURPOSE:To distinguish an in-device generated empty cell from other cells by newly generating an empty cell at the time of transfer of timing and outputting specific information. CONSTITUTION:A write address control circuit 16 inputs a transmission line extraction timing signal 3 and controls operation for writing a cell in a cell buffer 12 according to a clock extracted from the reception signal of an ATM transmission line. Further, a phase supervisory and control circuit 17 is equipped with a means which monitors the phase of write timing and inserts an empty cell when there is no cell stored in the cell buffer 12 or when a cell buffer number becomes less than a predetermined numeral. Then an emptiness marker adding circuit 13 outputs information indicating a generated empty cell when the phase supervisory and control circuit 17 newly generates the empty cell. The phase supervisory and control circuit 17 and emptiness marker adding circuit 13 are provided with an empty cell generating means and a monitor means which outputs information for distinguishing the in-device empty cell from other cells.

5. 发明专利

JPH03229537A METHOD AND EQUIPMENT FOR TRANSMITTING INFORMATION 失效
公开(公告)号：JPH03229537A
公开(公告)日：1991-10-11
申请号：JP2397190
申请日：1990-02-02
申请人： NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD , NEC CORP
发明人： UEDA HIROMI , FUJIME KAZUHIRO , NAKANO YUKIO , MURAKAMI KOU
IPC分类号： H04L5/22 , H04J3/00
摘要： PURPOSE:To transmit a payload with small delay even if the transmission line of small transmission capacity is included by constituting a pointer so that it instructs the frame of a virtual container at every S frames (S is integer of >=2). CONSTITUTION:In a transmission method which is to set the phase relation between the frame and information to be independent and to transmit it by using the pointer, a processing part 1 processes the part of section overhead and supplies two among three administrative units AU-32 to AU-32 pointer reception parts 2 and 3 one by one. The reception parts 2 and 3 detect positions in the frame of the leading byte of the virtual container VC-32 and transmit the information to shortening pointer generation parts 6 and 7 and remaining parts to bus overhead shortening parts 4 and 5. The shortening parts 4 and 5 reduce and shorten the number of the bytes of VC-32 bus overhead and the generation parts 6 and 7 write the position of the leading byte of shortening VC-32 in the frame into the shortening AU-32 pointer. A section overhead generation part 8 adds section overhead to two shortening AU-32 and generates the frame.

6. 发明专利

JPH08331142A VIRTUAL PATH SWITCHING SYSTEM 失效
公开(公告)号：JPH08331142A
公开(公告)日：1996-12-13
申请号：JP13531495
申请日：1995-06-01
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： KOYANAGI TOSHINORI , IGUCHI KAZUO , OTA HIROSHI , UEMATSU HITOSHI , UEDA HIROMI , ASHI MASAHIRO , NAKANO YUKIO , TAKATORI MASAHIRO
IPC分类号： H04L1/22 , H04L7/00 , H04L12/28 , H04L12/70 , H04L12/709 , H04L12/713 , H04Q3/00
摘要： PURPOSE: To perform switching from a current virtual path to a standby virtual path. CONSTITUTION: A cell for switching is inserted to the same positions of the current virtual path and the standby virtual path by a transmitter 20, and a cell for switching control on either side of the current virtual path or the standby virtual path is detected by a receiver 30. The cell on one side is stored in a phase absorption buffer 48, and the cell for switching control on the path on the other side is detected, and the cell string of the current virtual path is switched to the one of the standby path read out or transmitted from the phase absorption buffer 48.

7. 发明专利

JPH05327777A SYNCHRONIZING METHOD FOR ATM SWITCH, AND ATM SWITCH 失效
公开(公告)号：JPH05327777A
公开(公告)日：1993-12-10
申请号：JP12357592
申请日：1992-05-15
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI MASAHIRO , NAKANO YUKIO , ASHI MASAHIRO , NAKAJIMA TAKASHI
IPC分类号： H04Q3/52 , H04L12/28 , H04L12/66 , H04Q11/04
摘要： PURPOSE:To more exactly realize the synchronization between plural switch elements in the ATM of a parallel processing type. CONSTITUTION:A reset cell generating part 3 generates a reset cell by an input timing of a cell from an input highway 1-1. A cell separating part 4-1 divides the reset cell into M pieces of divided cells, and sends simultaneously each divided cell to switch elements 5-1-5-M. The switch elements 5-1-5-M detect the divided cell formed by dividing the reset cell, and initialize themselves by synchronizing therewith.

8. 发明专利

JPH03153136A FRAME PHASE CONVERSION METHOD AND FRAME PHASE CONVERSION CIRCUIT 失效
公开(公告)号：JPH03153136A
公开(公告)日：1991-07-01
申请号：JP29099789
申请日：1989-11-10
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI MASAHIRO , NAKANO YUKIO , ISHIDA KEIICHI , MORI TAKASHI , ASHI MASAHIRO , SUGANO TADAYUKI , UEDA HIROMI
IPC分类号： H04J3/00 , H04J3/06 , H04L7/00 , H04Q11/04
摘要： PURPOSE:To warrant TSSI(Time Slet Sequence Integrity) between signals via a same transmission line by using a control method for phase conversion buffer between plural signals in common and selecting a sole state for stuffing no phase conversion buffer to transmit plural signals while keeping mutual frame phase difference. CONSTITUTION:A memory is divided into an ES and a buffer and one memory overrides clocks. Then analog discrimination as to whether or not twice reading or skip of the ES for wonder absorption is to be executed is implemented by one phase comparator. Thus, stuff is generated simultaneously in AU-32#1-#3 and the stuffing is executed at a post-stage buffer. Thus, the transmission is attained while providing a frame phase among the AU-32. Moreover, independent frame phase conversion is attained to an input signal having an independent frame phase.

9. 发明专利

JPH0364197A LINE SETTING DEVICE FOR MULTIPLE ACCESS SPEED 失效
公开(公告)号：JPH0364197A
公开(公告)日：1991-03-19
申请号：JP19943389
申请日：1989-08-02
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKANO YUKIO , ASHI MASAHIRO , UEDA HIROMI
IPC分类号： H04Q11/04 , H04L12/50 , H04L12/52
摘要： PURPOSE:To attain line setting while a signal of a data part and a signal of the entire transmission frame exist in mixture by providing a circuit supplying the data part to a switch and a circuit converting the entire frame into a signal with an integer multiple of the switching unit. CONSTITUTION:First means 220-223, 240-243 receive a signal from a transmission line, eliminate a control bit and output the result to a time division switch 101, while 2nd means 230-233 receive and extracts the data from a time division switch 101, add the control bit and output the result to a transmission line. Third means 200-203 add a surplus bit to a signal received from the transmission line and output the result to the time division switch 101 and 4th means 210-213 eliminate the surplus bit from the signal received from the time division switch 101 and output the result to the transmission line. The time division switch 101 applies line setting in the unit of kX64kb/s (k is an integer equal to and larger than 2) among plural switch highways. Thus, the line setting is attained while a signal of a data part and a signal of the entire transmission frame exist in mixture.

10. 发明专利

JPH08237253A METHOD AND DEVICE FOR SWITCHING VIRTUAL PATH OF ATM NETWORK 失效
公开(公告)号：JPH08237253A
公开(公告)日：1996-09-13
申请号：JP3637195
申请日：1995-02-24
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKATORI MASAHIRO , NAKANO YUKIO , ASHI MASAHIRO , UEDA HIROMI , UEMATSU HITOSHI , OTA HIROSHI
IPC分类号： H04L1/22 , H04L12/28 , H04Q3/00
摘要： PURPOSE: To realize synchronous switching without a hit at the time of switching active and stand by virtual paths(VPs) in an ATM network where the active and stand-by (VPs) are set duplicately. CONSTITUTION: Switch control OAM cells to which a sequence numbers and the identification codes for switch 'necessity' or 'unnecessity' are intermittently transmitted from the switch control OAM cell generation/insertion circuit 1-1 of a transmission node 1 to duplex VPs (VP10T and VP11T). The VP switch control part 2-1 of a receiving node 2 uses the identification code for switch 'necessity' or 'unnecessity' of the switch control OAM cell and collates the sequence number by both VPs. Thus, a delay difference and the loss of the switch control OAM cell are detected, and VP establishing synchronism is switched. The switching of plural active and stand-by VPs is independently controlled. No-hit switching is realized by means of plural VP, and the addresses of the cells stored in a synchronism establishment buffer memory are controlled for respective VPs. Thus, VP can independently be switched.

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