专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH06237265A 0/1 SYSTEM SWITCHING METHOD WITHOUT SHORT BRAKE IN ATM COMMUNICATION SYSTEM 失效
公开(公告)号：JPH06237265A
公开(公告)日：1994-08-23
申请号：JP2383193
申请日：1993-02-12
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： SATOU MUTSUMI , UEDA HIROMI , OTA HIROSHI
IPC分类号： H04L1/22 , H04J3/00 , H04L12/28 , H04L12/48
摘要： PURPOSE:To realize the O/1 system switching method without short break which compares phases of user cell numbers to always match the phases of user cells in the ATM communication system of the SDH base. CONSTITUTION:A user cell number from a user cell number adding part 9 is added to the first user cell by transmission format conversion parts 7 and 8 on the transmission side. The first user cell number is extracted by a phase deviation detecting part 2 on the reception side, and numbers of respective user cells are reproduced to detect the phase system between both systems. This phase difference detection signal is sent to system 0 and system 1 reception format conversion parts 3 and 4, and the ATM output signal on the leading phase side is delayed to match the phases of both systems. A SEL part 1 receives ATM signals, whose phases are matched, to perform switching without short break.

2. 发明专利

JPH06132970A TRANSMISSION QUALITY MONITORING SYSTEM 失效
公开(公告)号：JPH06132970A
公开(公告)日：1994-05-13
申请号：JP27758892
申请日：1992-10-16
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： KURANO TAKANORI , NISHIHARA MOTOO , UEDA HIROMI , OTA HIROSHI
IPC分类号： H04L12/28 , H04L12/48
摘要： PURPOSE:To suppress the increase of traffic caused by insertion of a monitoring use cell at the time of the normal state and at the same time to secure the monitoring ability at the time of the deterioration state. CONSTITUTION:A 1st BIP computing part 111 calculates the bit interleave parities at every virtual path or channel and for every certain number of cells and outputs the calculated parities as the 1st computing results. A monitoring cell inserting part 115 inserts the monitoring cell storing the 1st computing results in the pay load into a transmission line. A monitoring use cell extracting part 118 extracts the monitoring cell out of the transmission line. Then a 2nd BIP computing part 117 calculates the bit interleave parities every certain number of cells of the correspondent virtual path or virtual channel that is sandwiched between the extracted monitoring cells and outputs the calculated parities at the 2nd computing results. Then a computing result comparing part 119 compares the 1st computing result with the 2nd one to monitor the bit error ratio and to vary a certain number of cells at every virtual path or channel.

3. 发明专利

JPH10303918A DIFFERENTIAL SERIES RETRIEVING CIRCUIT, RTS COMPLEMENTARY CIRCUIT AND RTS COMPLEMENTING DEVICE 失效
公开(公告)号：JPH10303918A
公开(公告)日：1998-11-13
申请号：JP11204197
申请日：1997-04-30
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： HIROKI NOBUYUKI , UEMATSU HITOSHI , OTA HIROSHI
IPC分类号： H04L7/08 , H04L12/28 , H04L12/70
摘要： PROBLEM TO BE SOLVED: To calculate the cycle of differential series without preliminarily knowing a clock differential series of a sending end by successively comparing shift differential series with n increased by one each. SOLUTION: When a differential series and shift differential series make n bits coincidence, n is made a differential series cycle by successively comparing the differential series with the shift differential series which shifts the differential series by n bits with n increased by one each. For instance, when a differential series is compares with shift differential series (1) to (4) when a sending clock fs =44.736 MHz+20 ppm, each upper stage is the original differential series, and the shift differential series on lower stages are acquired by shifting the the upper stages with n=2 to 5 respectively. In the series (1) to (3), because there is no n bits coincidence, any of them is not decided as a differential series cycle. In the series (4), n=5 and also the differential series and the shift differential series make 5 bits coincidence. Therefore, it is decided that a differential series cycle T=5.

4. 发明专利

JPH0774755A PHASE MATCHING DEVICE FOR CELL OF ACTIVE AND STANDBY SYSTEM IN ATM COMMUNICATION SYSTEM 失效
公开(公告)号：JPH0774755A
公开(公告)日：1995-03-17
申请号：JP24035593
申请日：1993-09-01
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： MIYAMOTO AKIHIRO , OTA HIROSHI , UEDA HIROMI
IPC分类号： H04J3/06 , H04J3/00 , H04L1/22 , H04L7/00 , H04L12/28
摘要： PURPOSE:To prevent disabic uninterruptible redundant changeover of transmission lines resulting from a deviated cell phase in both an active and a standby system when an idle cell is inserted in both the active and a standby system in an ATM cell format converter. CONSTITUTION:When an underflow of format conversion buffers 11A, 11B is detected by detection circuits 12A, 12B, its detection output is sent to other system. Idle cell insert control circuits 14A, 14B make idle cell command to idle cell insert circuits 13A, 13B of a concerned system to avoid a cell phase shift between both the systems when a detection output (idle cell insert command) is sent from the concerned system and other system.

5. 发明专利

JPH10271122A CLOCK REPRODUCING DEVICE 失效
公开(公告)号：JPH10271122A
公开(公告)日：1998-10-09
申请号：JP7315797
申请日：1997-03-26
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： YAMADA KENSHIN , OTA HIROSHI
IPC分类号： H04L7/00 , H04L7/02 , H04L12/28 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To provide a clock reproducing device with which clock reproduction control is possible corresponding to the state of regenerative clock. SOLUTION: This clock reproducing device is provided with a DSP 2 which has an internal program and inputs information corresponding to the phase difference component of the write clock and the read clock. When the information corresponding to the phase difference component is inputted according to the internal program, the DSP 2 selects any suitable parameter for control or processing algorithm corresponding to the state of generating the read clock and with the selected parameter for control or processing algorithm, the control of clock generation is performed.

6. 发明专利

JPH0774756A PHASE MATCHING DEVICE FOR BYTE OF TRANSMISSION DATA FOR BOTH ACTIVE AND STANDBY SYSTEM IN ATM COMMUNICATION SYSTEM 失效
公开(公告)号：JPH0774756A
公开(公告)日：1995-03-17
申请号：JP24035693
申请日：1993-09-01
申请人： NEC CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： MIYAMOTO AKIHIRO , OTA HIROSHI , UEDA HIROMI
IPC分类号： H04J3/06 , H04J3/00 , H04L1/22 , H04L7/00 , H04L12/28
摘要： PURPOSE:To attain uninterruptible redundancy changeover of a transmission line by making cell phases of transmission data in an SDH frame at changeover of active/standby system in data transmission to a transmission line in the ATM system. CONSTITUTION:A cell position byte number measurement circuit 3A detects a cell head position from an overhead of read data by a format conversion buffer 1A in an active system A and the cell position corresponding to a detected by the number is informed to a standby system B. When the standby system B is selected, a cell pulse generating circuit 5B of the standby system decides a cell pulse generating timing of the cell pulse generating circuit 2B according to the noticed cell position byte number to control read of the buffer 2B. Thus, the phases of the cells of both the systems are matched with each other at redundant changeover and uninterruptible changeover is attained.

7. 发明专利

JPH05292118A 失效
公开(公告)号：JPH05292118A
公开(公告)日：1993-11-05
申请号：JP9468292
申请日：1992-04-15
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , NEC CORP , HITACHI LTD
发明人： TANIGUCHI IKUO , HANAOKA SUSUMU , OTA HIROSHI , UEDA HIROMI , KURANO TAKANORI , NISHIHARA MOTOO , ASHI MASAHIRO , NAKANO YUKIO
IPC分类号： H03M13/00 , H04L12/24 , H04L12/26 , H04L12/48
摘要： PURPOSE:To reduce the scale of the circuit and to decrease a delay in a line with respect to the transmission quality supervisory system in the transmitter/ receiver and communication system for the communication employing the ATM system. CONSTITUTION:A transmitter 310 is configured such that when a user cell number reaches a required number and an idle cell detection section 220 detects an idle cell, an output section 105 inserts the result from the calculation for error supervision for each transmission path (VP) at a transmission arithmetic operation section 100 to an idle cell based on a control signal outputted from a cell number variable control section 250 and sends the result as a supervisory OAM cell. Furthermore, a receiver 320 uses an error discrimination section 200 to compare the result obtained by the arithmetic operation for error supervision as to a block separated by an OAM cell received by a reception arithmetic operation section 110 with the result of arithmetic operation extracted from the OAM cell received by a reception information extract section 180 thereby implementing error supervision to a cell string of variable length.

8. 发明专利

JPH1075248A SWITCHING CIRCUIT 失效
公开(公告)号：JPH1075248A
公开(公告)日：1998-03-17
申请号：JP22886996
申请日：1996-08-29
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： OTA HIROSHI
IPC分类号： H04L1/22 , H04B1/74 , H04L12/28 , H04L12/70 , H04L12/707 , H04L12/711 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To change virtual paths to other transmission lines altogether by changing the setting of a routing table at the time of the input of a switching instruction from the outside and performing changeover from the transmission line of a switching origin to the transmission line of a switching destination by respective cross-connection devices opposing each other through a plurality of transmission lines. SOLUTION: When a switching command is inputted from a host device 20 in the cross-connection devices 21 and 22, in the routing table 13-1, the virtual path of the transmission line 37 is retrieved from an output VPI(virtual path identifier), the virtual path of the transmission line 38 is retrieved from an input VPI, the transmission line 37 is rewritten to the transmission line 39 and the transmission line 38 is rewritten to the transmission line 40. Also, in the cross-connection device 22, the transmission line 38 is rewritten to the transmission line 40 and the transmission line 37 is rewritten to the transmission line 39. When the rewrite of the routing tables 13-1 and 13-2 is ended, the cross- connection devices 21 and 22 are turned to the reception standby state of the switching command from the host device again and the setting of the virtual paths is changed altogether.

9. 发明专利

JPH0993209A ALARM PROCESSING UNIT 失效
公开(公告)号：JPH0993209A
公开(公告)日：1997-04-04
申请号：JP24401795
申请日：1995-09-22
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKIZAWA YUJI , SATO HIROYUKI , MARUYAMA AKIRA , OTA HIROSHI
IPC分类号： H04B1/74 , H04B17/00
摘要： PROBLEM TO BE SOLVED: To distinguish alarm transfer during selection from other alarm transfer representing failed selection or a fault cause in the alarm processing unit that transfers information of a selection state by a selector to a downstream side. SOLUTION: The processing unit is provided with a before-selection state detection means 1 detecting the presence of a fault in a signal sent on transmission lines at a receiver side in duplicate and a switching state notice means 2 that generates information representing which of the transmission lines of the receiver side a selector selects depending on the detection result and transfers the information to a downstream.

10. 发明专利

JPH07147569A INSERTION CIRCUIT FOR MONITOR DATA 失效
公开(公告)号：JPH07147569A
公开(公告)日：1995-06-06
申请号：JP29229893
申请日：1993-11-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HASEGAWA HITOSHI , TANIGUCHI IKUO , OTA HIROSHI , UEDA HIROMI
IPC分类号： H04J3/12 , H04J3/14
摘要： PURPOSE:To maximize number of data insertion circuits within a predetermined time by inserting monitor data within a predetermined period and keeping an entire average monitoring data insertion period to be a predetermined period of a valid frame. CONSTITUTION:The circuit has a count section 10, a data insertion section 30, and an alarm detection section 20, the count section 10 receives an enable signal and a data insertion end flag and outputs carry-out for each N-th valid frame and sends a data insertion enable flag set for each N valid frame or cleared in a data insertion end flag. The data insertion section 30 receives the data insertion enable flag and inserts monitor data to a first idle frame while the data insertion enable flag continues the set state and sends the data insertion end flag. The alarm detection section 20 outputs an alarm set when carry-out is received when the data insertion enable flag is set and cleared when the data insertion end flag is received.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式