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1. 发明专利

JP2007096337A Wiring substrate for mounting semiconductor, semiconductor package, and its manufacturing method 审中-公开
标题翻译：用于安装半导体的接线基板，半导体封装及其制造方法
公开(公告)号：JP2007096337A
公开(公告)日：2007-04-12
申请号：JP2006313640
申请日：2006-11-20
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting semiconductor which is effective for the high integration of a semiconductor device, high speed, or increase in terminal by multifunction, and the narrow pitch of a distance between terminals, in which the semiconductor device can be mounted with high density and high accuracy specifically on the both surfaces of a substrate, and which is excellent also in reliability, its manufacturing method, and a semiconductor package.
SOLUTION: A wiring substrate 5 for mounting semiconductor is a wiring substrate comprising at least an insulating film 1, wiring 2 formed in the insulating film 1, and a plurality of electrode pads 4 conducted by the wiring 2 and a via 3. The electrode pad 4 is prepared on the front and back surfaces of the insulating film 1 such that the front surface is exposed. At least a part of the side surface of the electrode pad is embedded in the insulating film 1. The insulating film 1 can be formed by forming the electrode pads 4 on two sheets of metal plates, laminating the insulating layer and the wiring on the electrode pad 4 and each metal plate, pasting the insulating layer together and unifying the layer, and removing the metal plate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体装置的布线基板，其有效用于半导体器件的高集成度，高速度或多功能的端子增加，以及端子之间的距离的窄间距，其中半导体器件可以特别地在基板的两个表面上高密度和高精度地安装，并且在可靠性，其制造方法和半导体封装中也是优异的。解决方案：用于安装半导体的布线基板5是至少包括绝缘膜1，形成在绝缘膜1中的布线2和由布线2和通孔3传导的多个电极焊盘4的布线基板。在绝缘膜1的前表面和后表面上制备电极焊盘4，使得前表面露出。电极焊盘的侧面的至少一部分嵌入在绝缘膜1中。绝缘膜1可以通过在两片金属板上形成电极焊盘4而形成，在电极上层压绝缘层和布线垫4和每个金属板，将绝缘层粘贴在一起并使层合并，并移除金属板。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2006351963A WIRING BOARD AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：JP2006351963A
公开(公告)日：2006-12-28
申请号：JP2005178452
申请日：2005-06-17
申请人： NEC CORP , NEC ELECTRONICS CORP
发明人： KIKUCHI KATSU , YAMAMICHI SHINTARO , MURAI HIDEYA , FUNAYA TAKUO , MAEDA TAKEHIKO , HONDA KOICHI , OGAWA KENTA , TSUKANO JUN
IPC分类号： H05K3/46 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a wiring board wherein the cross-sectional shape of each of vias adopts a shape comprising parts of similar figures overlapped with each other so as to reduce hindrance to high density processing, to effectively increase the cross sectional area of the vias, and to prevent increase in the wiring resistance thereby realizing stable operations of semiconductor elements and to provide a manufacturing method thereof. SOLUTION: The wiring board on which the semiconductor elements or electronic components are mounted includes a plurality of wiring layers 11, 13, insulating layers 12 each provided between the wiring layers 11, 13, and the vias 16 provided to the insulation layers 12 to electrically connect the wiring layers 11, 13. In this wiring board, the cross-sectional shape of each via 16 shown on a plane in parallel with the wiring layers 11, 13 indicates the similar figures (circles) parts of which are overlapped. COPYRIGHT: (C)2007,JPO&INPIT

3. 发明专利

JP2006179952A Manufacturing method of wiring board for mounting semiconductor, and manufacturing method of semiconductor apparatus 有权
标题翻译：用于安装半导体的接线板的制造方法和半导体器件的制造方法
公开(公告)号：JP2006179952A
公开(公告)日：2006-07-06
申请号：JP2006068413
申请日：2006-03-13
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2924/15312 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide manufacturing methods of a wiring board for mounting a semiconductor and of a semiconductor apparatus which are effective for the increase in terminals and the fine-pitch of terminal gaps due to high-integration, high-speed, and multi-functionalization of semiconductor devices, can mount semiconductor devices especially on both surfaces of a board in a high density and with a high precesion, and is further excellent in reliability. SOLUTION: The wiring board 5 comprises at least an insulation film 1, wiring 2 formed in the insulation film 1, and a plurality of electrode pads 4 which are made mutually conductive by the wiring 2 and vias 3. The electrode pads 4 are disposed on the front and back surfaces of the insulation film 1 with the surfaces of the pads exposed and at least a part of the sides of the electrode pads embedded in the insulation film 1. The insulation film 1 is formed by forming respective electrode pads 4 on two metal sheets, stacking insulation layers and wiring on the electrode pads 4 and the metal plates, laminating, and integrating the insulation layers, and then removing the metal sheets. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供用于安装半导体的布线板和半导体装置的制造方法，其对于增加端子和由于高集成度而导致的端子间隙的微细间距高效率和半导体器件的多功能化，可以以高密度和高密度安装半导体器件，特别是在板的两个表面上，并且其可靠性更好。解决方案：布线板5至少包括绝缘膜1，形成在绝缘膜1中的布线2和由布线2和通孔3相互导电的多个电极焊盘4.电极焊盘4 设置在绝缘膜1的前表面和后表面上，其中焊盘的表面暴露，并且电极焊盘的至少一部分侧面嵌入绝缘膜1中。绝缘膜1通过形成相应的电极焊盘 4的两个金属片，堆叠绝缘层和电极焊盘4和金属板上的布线，层压并整合绝缘层，然后去除金属片。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2007027706A Wiring board, manufacturing method therefor and semiconductor package 有权
标题翻译：接线板及其制造方法及半导体封装
公开(公告)号：JP2007027706A
公开(公告)日：2007-02-01
申请号：JP2006168083
申请日：2006-06-16
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： YAMAMICHI SHINTARO , KIKUCHI KATSU , MURAI HIDEYA , FUNAYA TAKUO , MAEDA TAKEHIKO , OGAWA KENTA , TSUKANO JUN , HONDA KOICHI
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18 , H05K1/11 , H05K3/28 , H05K3/40 , H05K3/42
CPC分类号： H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/351 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a wiring board having superior reliability which is effective for the increase in the number of terminals and narrowing of a pitch between the terminals due to high integration, in higher speed and multifunction of a semiconductor device, and further superior in reliability. SOLUTION: In a recessed part 7a formed on one surface of a base substrate insulating film 7, a lower layer wiring comprising the wiring body 6 and an etching barrier layer 5 is formed, meanwhile, an upper layer wiring 11 is formed on the other surface of the base substrate insulating film 7, and further, the wiring body 6 of the lower layer wiring and the upper layer wiring 11 are connected to each other via a via hole 10 formed in the base substrate insulating film 7, in the wiring substrate 13. In this wiring substrate 13, the shape of the via hole 10 is to be made into a barrel shape, a bell shape or a bellows shape. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种具有优异的可靠性的布线板，对于半导体器件的更高速度和多功能性而言，由于高集成度，端子数量的增加和端子之间的间距变窄是有效的，进一步提高了可靠性。解决方案：在形成在基底绝缘膜7的一个表面上的凹部7a中，形成包括布线体6和蚀刻阻挡层5的下层布线，同时形成上层布线11 基底绝缘膜7的另一个表面，并且下层布线的布线体6和上层布线11经由形成在基底绝缘膜7中的通孔10彼此连接，布线基板13.在该布线基板13中，通孔10的形状为筒状，钟形或波纹状。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006024752A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006024752A
公开(公告)日：2006-01-26
申请号：JP2004201648
申请日：2004-07-08
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MIYAZAKI TAKASHI , FUNAYA TAKUO
IPC分类号： H01L25/18 , H01L21/56 , H01L21/60 , H01L25/065 , H01L25/07
CPC分类号： H01L24/10 , H01L21/563 , H01L24/13 , H01L24/28 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/16145 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/81141 , H01L2224/83102 , H01L2224/92125 , H01L2225/0651 , H01L2225/06513 , H01L2225/06582 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor chip with high reliability having a reinforcing bump structure which can resin-seal between chips. SOLUTION: In a slave chip 101 and a parent chip, the passage of a sealing resin 104 is provided between the region in which a slave chip 102 is provided and the periphery of the slave chip 101. Consequently, the flowing velocity of the sealing resin can be substantially made uniform. Therefore, the generation of any void in the sealing resin 104 can be suppressed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有可在芯片之间树脂密封的加强凸块结构的具有高可靠性的半导体芯片。解决方案：在副芯片101和母芯片中，密封树脂104的通道设置在设置有从芯片102的区域和从芯片101的周围之间。因此，流动速度密封树脂可以基本上均匀。因此，可以抑制密封树脂104中的任何空隙的产生。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2009004813A Wiring substrate for mounting semiconductor 审中-公开
标题翻译：用于安装半导体的接线基板
公开(公告)号：JP2009004813A
公开(公告)日：2009-01-08
申请号：JP2008243381
申请日：2008-09-22
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12 , H05K3/46
CPC分类号： H01L2221/68345 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting semiconductor which is effective for the high integration of a semiconductor device, high speed, or increase in terminal by multifunctionalities, and the narrow pitch of a distance between terminals, in which the semiconductor device can be mounted at high density and high accuracy, specifically on both the surfaces of a substrate, and which is superior also in reliability. SOLUTION: The wiring substrate 5 for mounting semiconductors includes, at least an insulating film 1, wires 2 formed in the insulation film 1, and a plurality of electrode pads 4 that electrically connect to the wires 2 through vias 3. The electrode pads 4 are provided, to have their surfaces exposed to both the front surface and the backside of the insulation film 1, and at least part of the side surface of the electrode pads is embedded in the insulating film 1. The insulating film 1 is formed, by forming electrode pads 4 on the respective two metal plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad 4, and making the insulation layers adhere to each other for integration, and thereafter, removing the metal plates. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体安装用布线基板，其能够通过多功能性实现半导体器件的高集成度，高速度或端子的增加，以及端子之间的距离的窄间距，其中半导体器件可以以高密度和高精度安装，特别是在基板的两个表面上，并且其可靠性也优异。解决方案：用于安装半导体的布线基板5至少包括绝缘膜1，形成在绝缘膜1中的布线2，以及多个通过通孔3电连接到布线2的电极焊盘4。提供垫4以使其表面暴露于绝缘膜1的前表面和后侧，并且电极焊盘的至少一部分侧表面被嵌入绝缘膜1中。形成绝缘膜1 通过在相应的两个金属板上形成电极焊盘4，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘4，并且使绝缘层彼此粘合以一体化，然后除去金属板。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2008306071A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008306071A
公开(公告)日：2008-12-18
申请号：JP2007153293
申请日：2007-06-08
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MORI KENTARO , YAMAMICHI SHINTARO , MURAI HIDEYA , FUNAYA TAKUO , KAWANO MASAYA , MAEDA TAKEHIKO , SOEJIMA KOJI
IPC分类号： H01L23/12
CPC分类号： H01L21/6835 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L24/24 , H01L2221/68345 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/15174 , H01L2924/15788 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , Y10S438/977 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving high density, thin shape and low cost, which achieves chip mounting with high precision, which needs no preparation of position marks on a base material at the time of chip mounting on the base material in a manufacturing process, and which can make removing of the base material easy, and a method for manufacturing the same. SOLUTION: A transparent substrate 23 is arranged on a support substrate 21 provided with position marks 22, and a lifting material 24 is provided thereon. On the lifting material 24, a semiconductor element 11 is arranged so that electrode elements 13 are upside, and, thereafter, the support substrate 21 is removed. Subsequently, after an insulating resin 12 is formed on the lifting material 24 so as to cover the semiconductor element 11, vias 14, a wiring layer 15, an insulating layer 16, external terminals 17 and a solder resist 18 are formed. Thereafter, the transparent substrate 23 is removed from the semiconductor device by the lifting material 24. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供能够实现高密度，薄形状和低成本的半导体器件，其实现了高精度的芯片安装，在芯片安装时不需要在基材上准备位置标记在制造工艺中的基材上，并且能够容易地除去基材，以及其制造方法。解决方案：在设置有位置标记22的支撑基板21上设置透明基板23，并且在其上设置提升材料24。在提升材料24上，配置半导体元件11，使得电极元件13是上侧，之后移除支撑基板21。随后，在提升材料24上形成绝缘树脂12以覆盖半导体元件11，通孔14之后，形成布线层15，绝缘层16，外部端子17和阻焊剂18。此后，透明基板23由提升材料24从半导体器件移除。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2006186396A WIRING SUBSTRATE FOR MOUNTING SEMICONDUCTOR 审中-公开
公开(公告)号：JP2006186396A
公开(公告)日：2006-07-13
申请号：JP2006068419
申请日：2006-03-13
申请人： NEC CORP , NEC ELECTRONICS CORP
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting semiconductor, which is effective in promoting higher integration of a semiconductor device, and in the increase of the number of terminals and in achieving a narrower pitch between the terminals according to faster speed or multi-functionalization, allows semiconductor devices especially to be mounted on both sides of the substrate with high density and with high precision, and is further excellent also in reliability, and also to provide its manufacturing method, and a semiconductor package. SOLUTION: This wiring substrate 5 for mounting semiconductor comprises an insulation film 1, wiring 2 formed in the insulation film 1, and a plurality of electrode pads 4 conductive with the wiring 2 through via-holes 3. The electrode pads 4 are formed with their surface exposing on both sides of the insulation film 1, and at least a part of the side surface of the electrode pads is buried in the insulation film 1. After the electrode pads 4 are formed on the respective two metal plates, the insulating layer and the wiring are laminated onto the electrode pads 4 and the respective metal plates, and then insulation film 1 is formed by laminating the insulating layers to each other to integrate them, and then by removing the metal plates. COPYRIGHT: (C)2006,JPO&NCIPI

9. 发明专利

JP2006049819A Wiring substrate for mounting semiconductor, its manufacturing method, and semiconductor package 有权
标题翻译：用于安装半导体的布线基板及其制造方法和半导体封装
公开(公告)号：JP2006049819A
公开(公告)日：2006-02-16
申请号：JP2005138450
申请日：2005-05-11
申请人： Nec Corp , Nec Electronics Corp , Necエレクトロニクス株式会社 , 日本電気株式会社
发明人： MURAI HIDEYA , ORITO NAONORI , FUNAYA TAKUO , KIKUCHI KATSU , YAMAMICHI SHINTARO , BABA KAZUHIRO , HONDA KOICHI , HO KEIICHIRO , MATSUI KOJI , MIYAZAKI SHINICHI
IPC分类号： H01L23/12
CPC分类号： H01L21/4857 , H01L23/49822 , H01L23/49833 , H01L23/5383 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/45144 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/181 , H05K3/007 , H05K3/205 , H05K3/28 , H05K3/4614 , H05K3/4682 , H05K2201/0376 , H05K2203/0152 , H05K2203/061 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate for mounting a semiconductor which is effective in the increase of terminal and close narrowness of space between terminals due to the high integration, high speedup, and multi-functionalization of a semiconductor device, and which can particularly mount semiconductors on both sides of the substrate in high density and with high accuracy, and which is excellent in reliability too; to provide its manufacturing method; and to provide a semiconductor package. SOLUTION: The wiring substrate 5 for mounting a semiconductor is composed of at least an insulating film 1, wiring 2 formed in the insulating film 1, and a plurality of electrode pads 4 connected with the wiring 2 and a via 3. The electrode pad 4 is located on both sides of the surface/back with the surface exposed, and at least a part of side of the electrode pad is buried in the insulating film 1. After the electrode pads 4 are formed on the two sheets of metal plate and then the insulating layer and wiring are laminated on the electrode pad 4 and each of metal plates, the insulating layer 1 is laminated to be united, then, the insulating layer 1 can be formed by removing the metal plate. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了提供一种用于安装半导体的布线基板，其由于半导体器件的高集成度，高加速度和多功能化而在端子间增加并且端子之间的空间狭窄，所以有效，并且可以以高密度和高精度特别地在基板的两侧上安装半导体，并且其可靠性也优异; 提供其制造方法; 并提供半导体封装。解决方案：用于安装半导体的布线基板5至少由绝缘膜1，形成在绝缘膜1中的布线2和与布线2和通孔3连接的多个电极焊盘4构成。电极焊盘4位于表面/背面的两侧，表面露出，并且电极焊盘的至少一部分侧面被埋在绝缘膜1中。在电极焊盘4形成在两片金属然后将绝缘层和布线层叠在电极焊盘4和每个金属板上，将绝缘层1层合在一起，然后通过去除金属板来形成绝缘层1。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2007128982A Semiconductor bump connection structure and its manufacturing method 有权
标题翻译：半导体保护连接结构及其制造方法
公开(公告)号：JP2007128982A
公开(公告)日：2007-05-24
申请号：JP2005318753
申请日：2005-11-01
申请人： Nec Corp , 日本電気株式会社
发明人： FUNAYA TAKUO , YAMAMICHI SHINTARO
IPC分类号： H01L21/607 , H01L21/60
CPC分类号： H01L2224/16 , H01L2224/16059 , H01L2224/16105 , H01L2224/16503 , H01L2224/29011 , H01L2224/73103 , H01L2224/73204 , H01L2924/01019 , H01L2924/01327 , H01L2924/09701 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor bump connection structure wherein appropriate connection can be ensured without using flux, the contact area of a solder bump with an electrode of an electronic part can be controlled to be specified at all times, and no shortcircuiting among the bumps occurs during reflow and of which a connection portion is superior in reliability, and to provide its manufacturing method. SOLUTION: In a flip-chip connection structure wherein an electrode 2 of a first electronic part and an electrode 6 of a second electronic part are connected by a solder bump 3, metal compound layers 4 and 7 are formed on a bonding boundary between the electrodes 2 and 6 of the solder bump 3, and a narrow part 10 is formed on the side surface of the solder bump 3, namely, on a host-phase side adjacent to an intermetallic compound layer in at least one bonding part on the sides of the first and second electronic parts. The narrow part 10 reduces stress generating due to the difference of thermal expansion coefficients, on the side of the solder host phase. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供半导体凸块连接结构，其中可以在不使用焊剂的情况下确保适当的连接，可以一直规定焊料凸块与电子部件的电极的接触面积，在回流期间不会发生短路，并且连接部的可靠性优异，并且提供其制造方法。解决方案：在第一电子部件的电极2和第二电子部件的电极6通过焊料凸块3连接的倒装芯片连接结构中，金属化合物层4和7形成在接合边界在焊料凸块3的电极2和6之间，并且在焊料凸块3的侧表面上，即在与金属间化合物层相邻的主相侧上的至少一个结合部分上形成窄部分10 第一和第二电子部件的侧面。狭窄部分10减少由于焊料主体相侧的热膨胀系数的差异产生的应力。版权所有（C）2007，JPO＆INPIT

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