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1. 发明专利

JP2010161696A Isolation circuit 审中-公开
标题翻译：隔离电路
公开(公告)号：JP2010161696A
公开(公告)日：2010-07-22
申请号：JP2009003321
申请日：2009-01-09
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI
IPC分类号： H03H7/09
摘要： PROBLEM TO BE SOLVED: To provide an isolation circuit perfectly separating the ground with one electronic circuit component connected thereto from the ground with the other electronic circuit component connected thereto in transmitting a signal in a high-frequency region, and transmitting not only the signal in the high-frequency region but also a signal in a low-frequency region.
SOLUTION: An analog-digital converter 110 and an FPGA 120 are mounted on a board 10. This isolation circuit 1 is formed between the analog-digital converter 110 and the FPGA 120. The isolation circuit 1 is used for electrically separating separate ground layers 11, 12 from each other, and includes a transformer 2 and ferrite beads 3-1, 3-2. The transformer 2 is used for transmitting only a high-frequency digital signal, and the ferrite beads 3-1, 3-2 are used for transmitting only a low-frequency digital signal.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种隔离电路，将地面与其上连接的另一个电子电路部件的地面连接的一个电子电路部件与高频区域中的信号进行传输，并且不仅传输高频区域的信号，也是低频区域的信号。解决方案：模拟数字转换器110和FPGA 120安装在电路板10上。该隔离电路1形成在模数转换器110和FPGA 120之间。隔离电路1用于电分离接地层11,12彼此之间，并且包括变压器2和铁氧体磁珠3-1,3-2。变压器2仅用于发送高频数字信号，铁氧体磁珠3-1,3-2仅用于发送低频数字信号。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010027999A Mounting structure of common mode choke coil 审中-公开
标题翻译：共同模式选择线圈的安装结构
公开(公告)号：JP2010027999A
公开(公告)日：2010-02-04
申请号：JP2008190514
申请日：2008-07-24
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI
IPC分类号： H01F17/00 , H01F27/29
摘要： PROBLEM TO BE SOLVED: To provide a mounting structure of a common mode choke coil which allows not only skew control between differential signals but also reduction in the unsharpness of each waveform of differential signals outputted from the common mode choke coil.
SOLUTION: The common mode choke coil 1 is mounted via a skew control circuit 2 in a differential transmission path 3. That is, external electrodes 7-1, 21, 22 (7-2, 23, 24) are connected to input side lead-out electrodes 51a, 52a, (53a, 54a) of a parallel coil 5-1 (5-2) at equal spacings d1 (d2). Land patterns 25, 26 (28, 29) are juxtaposed at a spacing d1 (d2) and connected to the end 31 (32) of lines 3-1 (3-2) using a pattern 27 (30). The external electrodes 7-1, 21, 22 (7-2, 23, 24) are arranged close to the end 31 (32) and the land patterns 25, 26 (28, 29) to connect the ends 31 (29) and the external electrodes 7-1 (24).
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种共模扼流线圈的安装结构，其不仅允许差分信号之间的偏移控制，而且还降低从共模扼流线圈输出的差分信号的每个波形的不清晰度。解决方案：共模扼流线圈1通过偏移控制电路2安装在差分传输路径3中。也就是说，外部电极7-1,21,22（7-2,23,24）连接到平行线圈5-1（5-2）的输入侧引出电极51a，52a，（53a，54a）以等间距d1（d2）。地面图案25,26（28,29）以间隔d1（d2）并列并且使用图案27（30）连接到线3-1（3-2）的端部31（32）。外部电极7-1,21,22（7-2,23,24）靠近端部31（32）和焊盘图案25,26（28,29）设置，以将端部31（29）和外部电极7-1（24）。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009010207A Common mode choke coil 有权
标题翻译：共用模式选择线圈
公开(公告)号：JP2009010207A
公开(公告)日：2009-01-15
申请号：JP2007170790
申请日：2007-06-28
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI , NISHIKAWA ZENEI , HIRAI MASAYA
IPC分类号： H01F17/04 , H01F27/00 , H03H7/09
CPC分类号： H01F17/045 , H01F2017/0093
摘要： PROBLEM TO BE SOLVED: To provide a common mode choke coil improved in immunity characteristics by forming its coil structure in to the one which can prevent malfunctions of a transmitting IC and a receiving IC at the time of an immunity test. SOLUTION: The common mode choke coil is provided with a core 2, outside electrodes 3-1 to 3-4, a pair of coils 4-1 and 4-2, and a top plate 5. The core 2 is composed of a winding core part 20 and flanges 21, 22. Also, the pair of coils 4-1 and 4-2 are wound around the winding core part 20 of the core 2, and ends of the coils 4-1 and 4-2 are connected to the outside electrodes 3-1 to 3-4, respectively. Furthermore, a resistance part 6 is interposed between a top plate 5 and the flanges 21, 22. This resistance part 6 is constituted by alternately laminating three layers of metal films 61-63 and two layers of magnetic plate pieces 51 and 52, and bonded to upper end surfaces of the flanges 21 and 22 with an adhesive 7. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供通过将线圈结构形成为能够防止在免疫测试时发射IC和接收IC的故障的共同模式扼流线圈来提高抗扰性特性。解决方案：共模扼流线圈设有芯体2，外部电极3-1至3-4，一对线圈4-1和4-2以及顶板5.芯体2组成卷绕芯部20和凸缘21,22的同时，一对线圈4-1和4-2缠绕在芯2的卷芯部20上，线圈4-1和4-2的端部分别连接到外部电极3-1至3-4。此外，电阻部分6介于顶板5和凸缘21,22之间。该电阻部分6通过交替层叠三层金属膜61-63和两层磁板片51和52而构成，使用粘合剂7到达凸缘21和22的上端表面。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008118078A Three-terminal capacitor 审中-公开
标题翻译：三端电容
公开(公告)号：JP2008118078A
公开(公告)日：2008-05-22
申请号：JP2006302530
申请日：2006-11-08
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI
IPC分类号： H01G4/35 , H01G4/30 , H01G4/38
摘要： PROBLEM TO BE SOLVED: To provide a three-terminal capacitor capable of removing high-frequency noise that appears on a high-frequency wave transmission line by reducing ESL as much as possible.
SOLUTION: The capacitor has a structure in which two grounding internal electrodes 2-1, 2-2 and one signaling internal electrode 3 are accommodated in a rectangular parallelepiped dielectric 10 and the signaling internal electrode 3 and a pair of signaling external electrodes 4-1, 4-2 are attached to the outside of the dielectric 10. Then, by connecting via holes 6-1 to 6-4 to the grounding internal electrodes 2-1, 2-2 and a grounding external electrode 5, the ESL of an entire three-terminal capacitor 1 is reduced. Preferably, the via holes 6-1, 6-3 (6-2, 6-4) are put as close as possible to the side of the signaling internal electrode 3.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够通过尽可能减少ESL来去除出现在高频波传输线上的高频噪声的三端电容器。解决方案：电容器具有两个接地内部电极2-1,2-2和一个信号内部电极3容纳在长方体电介质10和信令内部电极3以及一对信令外部电极中的结构 4-1，4-2安装在电介质10的外侧。然后，通过将通孔6-1〜6-4连接到接地内部电极2-1,2-2和接地外部电极5，整个三端电容器1的ESL减小。优选地，通孔6-1,6-3（6-2,6-4）尽可能靠近信号内部电极3的侧面。（C）2008，JPO和INPIT

5. 发明专利

JP2007036416A Noise-eliminating circuit structure and noise-eliminating method 审中-公开
标题翻译：噪声消除电路结构和噪声消除方法
公开(公告)号：JP2007036416A
公开(公告)日：2007-02-08
申请号：JP2005213773
申请日：2005-07-25
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI
IPC分类号： H03H7/09 , H03H7/01
摘要： PROBLEM TO BE SOLVED: To provide a noise-eliminating circuit structure and a noise-eliminating method for eliminating normal mode noise efficiently, by giving a directional property to reflection characteristics in a common mode choke coil.
SOLUTION: There are provided a transmitter 1, a receiver 2, a transmission path 3, and the common mode choke coil 4 mounted to the input section of the receiver 2. The directional property is given to the reflection characteristics of the common mode choke coil 4 to a high-frequency signal. Concretely, the reflection coefficient of the common mode choke coil 4 seen from the side of external electrodes 41a, 42a is set to be small, and that seen from the side of external electrodes 41b, 42b is set to be large, thus reflecting the normal mode noise returning from the side of a receiver IC21 in the receiver 2 by the common mode choke coil 4.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过给共模扼流线圈中的反射特性给出方向性，提供有效地消除正常模式噪声的噪声消除电路结构和噪声消除方法。解决方案：提供了一个发射机1，一个接收机2，一个传输路径3和安装在接收机2的输入部分上的共模扼流线圈4.定向特性被赋予了共同的反射特性模式扼流圈4到高频信号。具体地说，从外部电极41a，42a侧观察的共模扼流线圈4的反射系数设定得较小，从外部电极41b，42b的侧面看，设定为较大，因此反映正常模式噪声通过共模扼流线圈4从接收器2中的接收器IC21的侧面返回。版权所有：（C）2007，JPO＆INPIT

6. 发明专利

JP2006114801A Common mode choke coil 审中-公开
标题翻译：共用模式选择线圈
公开(公告)号：JP2006114801A
公开(公告)日：2006-04-27
申请号：JP2004302509
申请日：2004-10-18
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI , YAMANAGA ISAO
IPC分类号： H01F27/00 , H01C7/10 , H01F17/00 , H01F37/00 , H03H7/09
摘要： PROBLEM TO BE SOLVED: To provide a common choke coil that employs a distributed constant element structure for a varistor to prevent the characteristic impedance from lowering, and takes countermeasures against surges without distorting the waveform of a differential signal. SOLUTION: This common choke coil has the first and second external electrodes 3-1 and 3-2, and the third and fourth external electrodes 3-3 and 3-4 in a chip body 2. The chip body 2 has a structure where the second coil block 6 is laminated on the first coil block 4 via a static protection layer 5. Concretely, the insulated layers 41 and 42 and coil pattern 43 are laminated on a magnetic substrate 40 to form a first coil block 4, and the static protection layer 5 formed using the varistor materials is laminated on the insulated layer 42, covering the entire coil pattern 43. Then, the coil pattern 60, insulated layers 61 and 62, and magnetic substrate 63 are laminated on the static protection layer 5 to form the second coil block 6. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种采用用于变阻器的分布常数元件结构的公共扼流圈，以防止特性阻抗降低，并且对抗浪涌采取对策而不使差分信号的波形失真。解决方案：该公共扼流线圈在芯片体2中具有第一外部电极3-1和第二外部电极3-2以及第三和第四外部电极3-3和3-4。芯片体2具有通过静电保护层5将第二线圈块6层叠在第一线圈块4上的结构。具体地，将绝缘层41,42和线圈图案43层压在磁性基板40上，形成第一线圈块4，使用变阻器材料形成的静电保护层5层叠在绝缘层42上，覆盖整个线圈图案43.然后，将线圈图案60，绝缘层61和62以及磁性基板63层叠在静电保护层5上以形成第二线圈块6.版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2012186251A Three-terminal capacitor, and mounting structure of the same 审中-公开
标题翻译：三端电容器及其安装结构
公开(公告)号：JP2012186251A
公开(公告)日：2012-09-27
申请号：JP2011047202
申请日：2011-03-04
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI
IPC分类号： H01G4/12 , H01G4/232 , H01G4/30
摘要： PROBLEM TO BE SOLVED: To solve the following problem: even if a conventional three-terminal capacitor is used as a bypass capacitor by using it in a non-through state, reduction of ESL is not sufficient and further reduction of ELS is required.SOLUTION: In a three-terminal capacitor 21, a through via 26 passing through a dielectric 22 in the thickness direction thereof is provided while making no electrical contact with a ground internal electrode 25 and making electrical contact with a through internal electrode 23. The both upper and lower end faces of the through via 26 are exposed to the surface of the dielectric 22 between input and output terminals 24a, 24b. Therefore, a return path reaching a ground plane layer 33 from a power supply plane layer 32 through capacitance by way of the through via 26 is newly formed between power supply line wiring patterns 31a, 31b and the ground plane layer 33 by using this three-terminal capacitor in the non-through state with the through via 26 connected to the power supply plane layer 32 and with an interval between the input and output terminals 24a, 24b short-circuited by the power supply plane layer 32.
摘要翻译：解决的问题为了解决以下问题：即使以非贯通状态使用传统的三端子电容器作为旁路电容器，ESL的降低也不足以进一步减少ELS 需要。解决方案：在三端电容器21中，设置穿过电介质22的厚度方向的通孔26，而不与接地内部电极25电接触并与通孔内电极23电接触通孔26的上下端面暴露于电介质22的输入端子24a和输出端子24b之间。因此，通过使用该三维电路，在电源线配线图案31a，31b和接地面层33之间新形成从电源面层32通过通孔26到达接地面层33的电容，端子电容器处于非通过状态，通孔26连接到电源平面层32，并且在由电源平面层32短路的输入和输出端子24a，24b之间的间隔。版权所有：（C）2012，JPO＆INPIT

8. 发明专利

JP2006128618A Wiring pattern structure for differential transmission path 有权
标题翻译：差分传输路线接线图形结构
公开(公告)号：JP2006128618A
公开(公告)日：2006-05-18
申请号：JP2005177861
申请日：2005-06-17
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： YAMANAGA ISAO , TANAKA KANJI
IPC分类号： H05K1/02 , H01P3/04
CPC分类号： H05K1/0256 , H01P5/02 , H05K1/0237 , H05K1/0259 , H05K1/181 , H05K2201/09227 , H05K2201/09236 , H05K2201/10022 , H05K2201/10189 , H05K2201/10689
摘要： PROBLEM TO BE SOLVED: To provide a wiring pattern structure for a differential transmission path by which a nearly uniform characteristic impedance can be obtained in the whole length of the differential transmission path, equal length wiring can be executed, and a pattern forming area can be reduced. SOLUTION: The structure is for the differential transmission paths 1-4 electrically connecting an integrated circuit element 300 on a printed wiring board 100 with a connector 310. Each differential transmission path 1 (2-4) is composed of a pair of first/second signal lines 1a, 1b (2a-4a, 2b-4b). Each first signal line 1a (2a-4a) and each second signal line 1b (2b-4b) are formed into a hook shape. A rectangular region B is demarcated between the first/second signal lines 1a, 1b (2a-4a, 2b-4b). First/second electrostatic protection elements 51, 52 are arranged in each region B. Preferably, continuous bent parts of the first/second signal lines 1a, 1b (2a-4a, 2b-4b) are rounded. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供差分传输路径的布线图案结构，通过该布线图案结构可以在差分传输路径的整个长度上获得几乎均匀的特征阻抗，可以执行等长的布线，并且形成图案形成面积可以减少。解决方案：该结构用于将印刷电路板100上的集成电路元件300与连接器310电连接的差分传输路径1-4。每个差分传输路径1（2-4）由一对第一/第二信号线1a，1b（2a-4a，2b-4b）。每个第一信号线1a（2a-4a）和每个第二信号线1b（2b-4b）形成为钩形。在第一/第二信号线1a，1b（2a-4a，2b-4b）之间划分矩形区域B. 第一/第二静电保护元件51,52布置在每个区域B中。优选地，第一/第二信号线1a，1b（2a-4a，2b-4b）的连续弯曲部分是圆形的。版权所有（C）2006，JPO＆NCIPI

9. 发明专利

JP2005216942A Laminated coil 审中-公开
标题翻译：层压线圈
公开(公告)号：JP2005216942A
公开(公告)日：2005-08-11
申请号：JP2004018579
申请日：2004-01-27
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI , YAMAMOTO TAKAHIRO
IPC分类号： H01F17/00
摘要： PROBLEM TO BE SOLVED: To provide a laminated coil in which a DC resistance value is not increased even when the number of turns in a coil is augmented in a limited chip size, and from which a high impedance is obtained.
SOLUTION: First type band-shaped coil conductor patterns 11a, 11b and 11c and via holes 21, 22, 23 and 24 for an inter-layer connection constitute spiral sections wound in one turn or more respectively at the places of virtual surfaces S1 and S2 vertical in the direction of the coil axis of the coil L1. The ends of the two spiral sections constituted at each place of the two adjacent virtual surfaces S1 and S2 are connected by a second type band-shaped coil conductor pattern 12 parallel in the direction of the coil axis of the coil L1.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使当线圈中的匝数以有限的芯片尺寸增加并且从其获得高阻抗时，提供其中直流电阻值也不增加的层叠线圈。解决方案：第一类型的带状线圈导体图案11a，11b和11c以及用于层间连接的通孔21,22,23和24分别构成在虚拟表面的位置上卷绕一圈或更多圈的螺旋部分 S1和S2在线圈L1的线圈轴方向垂直。在两个相邻虚拟表面S1和S2的每个位置处构成的两个螺旋部分的端部通过在线圈L1的线圈轴线方向上平行的第二类型带状线圈导体图案12连接。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2011165776A Three-terminal capacitor and method of mounting the same 审中-公开
标题翻译：三端电容器及其安装方法
公开(公告)号：JP2011165776A
公开(公告)日：2011-08-25
申请号：JP2010024866
申请日：2010-02-05
申请人： Murata Mfg Co Ltd , 株式会社村田製作所
发明人： TANAKA KANJI
IPC分类号： H01G4/12 , H01G4/30 , H01G4/35
摘要： PROBLEM TO BE SOLVED: To provide a three-terminal capacitor, along with a method of mounting the same, capable of preventing a short circuit between lands in a mounting part, and capable of enhancing the mounting quality.
SOLUTION: The three-terminal capacitor 1-1 includes a chip 2 involving a through-electrode 3 and ground electrodes 4-1 and 4-2, external electrodes 5-1 and 5-2, and a ground external electrode 6. Further, the central part of the three-terminal capacitor 1-1 is provided with a through-bore 7 penetrating the central part of the ground external electrode 6 and the chip 2. By this arrangement, when such a situation that a solder 300 is lifted up from a through-hole 210 is caused, the lifted-up solder is allowed to escape into the through-bore 7, thereby preventing short circuit between a ground-side connecting land and a hot-side connecting land in which the three-terminal capacitor 1-1 is mounted.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供三端电容器及其安装方法，能够防止安装部件中的焊盘之间的短路，并且能够提高安装质量。解决方案：三端电容器1-1包括包括通电极3和接地电极4-1和4-2，外部电极5-1和5-2以及接地外部电极6的芯片2 此外，三端电容器1-1的中央部设置有贯穿接地外部电极6和芯片2的中心部的贯通孔7.通过这种布置，当焊料300 从通孔210被提起时，提起的焊料被允许逸出到通孔7中，从而防止接地侧连接区域和热侧连接区域之间的短路，其中三 - 端子电容器1-1。版权所有（C）2011，JPO＆INPIT

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