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1. 发明专利

JP2010177576A Semiconductor device manufacturing method and apparatus for correcting semiconductor package deformation 有权
标题翻译：半导体器件制造方法和校正半导体封装变形的装置
公开(公告)号：JP2010177576A
公开(公告)日：2010-08-12
申请号：JP2009020666
申请日：2009-01-30
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： SHIMIZU KOJI , NARIMATSU HIROAKI
IPC分类号： H01L21/56
摘要： PROBLEM TO BE SOLVED: To prevent product failures in a step of mold curing a package sealing resin in a resin-sealed semiconductor device.
SOLUTION: In a semiconductor device manufacturing method that includes a step of correcting deformation of semiconductor packages 6 by alternately placing the semiconductor packages 6, in each of which a semiconductor device is resin-sealed, and insertion plates 5, each of which is formed of a heat resistant flat plate, to stack them on a base 1, heating the semiconductor packages 6 to a predetermined temperature under a pressure applied with a weight 3 disposed on the uppermost insertion plate 5, and gradually lowering the temperature, the insertion plate 5 has on its surface counterbores or through-holes corresponding to the outlines of the external terminals and die pads of the semiconductor package 6 in contact with the insertion plate 5. Accordingly, the insertion plate 5 is placed not in contact with the external terminals and the die pads, completely eliminating flaws and foreign matters, which would otherwise be generated during the mold curing, and thereby improving yield.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了防止树脂密封半导体器件中的封装密封树脂模制固化的步骤中的产品故障。解决方案：在一种半导体器件制造方法中，包括通过交替放置半导体封装6的半导体封装6的变形来校正半导体封装6的变形的步骤，其中半导体器件被树脂密封，以及插入板5 由耐热平板形成，将它们堆叠在基座1上，在施加有设置在最上面的插入板5上的重物3的压力下将半导体封装6加热到预定温度，并逐渐降低温度，插入板5的表面具有与插入板5接触的与半导体封装6的外部端子和芯片焊盘的外形线对应的表面沉孔或通孔。因此，插入板5不与外部端子接触和模垫，完全消除了在模具固化期间将产生的缺陷和异物，从而提高了产量。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2010141175A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010141175A
公开(公告)日：2010-06-24
申请号：JP2008316750
申请日：2008-12-12
申请人： Mitsui High Tec Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社三井ハイテック
发明人： KADOGUCHI TAKUYA , SHIMIZU KOJI
IPC分类号： H01L23/12
CPC分类号： H01L24/73 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which thermal and electric connections between a heat sink and a mounting substrate are improved.
SOLUTION: The semiconductor device includes the mounting substrate 10 having a metal portion 11 patterned for heat dissipation and wiring, arrayed on a mounting surface, the heat sink 20 mounted on the mounting substrate 10 and connected to the metal portion 11, and a semiconductor element 30 mounted on the heat sink 20. The heat sink 20 has a plurality of solder mounting areas arranged in an area array on the side of the mounting surface 10A of the mounting substrate 10, and the heat sink 20 and mounting substrate 10 are connected to each other by fusing and connecting a first solder portion 26 arranged in the solder mounting area and a second solder portion 16 arranged at the metal portion 11 to each other.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其中散热器和安装基板之间的热和电连接被改善。解决方案：半导体器件包括安装基板10，其具有图案化用于散热和布线的金属部分11，排列在安装表面上，安装在安装基板10上并连接到金属部分11的散热器20以及安装在散热器20上的半导体元件30.散热器20具有在安装基板10的安装面10A的侧面上以区域阵列布置的多个焊料安装区域，散热器20和安装基板10 通过将布置在焊料安装区域中的第一焊料部分26和布置在金属部分11处的第二焊料部分16熔合并连接而彼此连接。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2010192695A Methods of manufacturing semiconductor device and lead frame of the same 审中-公开
标题翻译：制造半导体器件及其引线框架的方法
公开(公告)号：JP2010192695A
公开(公告)日：2010-09-02
申请号：JP2009035662
申请日：2009-02-18
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： SHIMIZU KOJI , NARIMATSU HIROAKI , KAI HIDEYOSHI
IPC分类号： H01L23/50
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide methods of manufacturing a semiconductor device and a lead frame of the semiconductor device, in which any plating burr generated by etching remains neither in the lead frame used as a product nor in the semiconductor device.
SOLUTION: The method is provided for manufacturing a semiconductor device 12 every unit lead frame region 10 in a lead frame raw material 11 in which a plurality of unit lead frame regions 10 are arranged at multiple columns or a single column, wherein after carrying out half etching of the lead frame raw material 11 from a front side thereof by using a first plating layer 24 as a resist film, there are provided an outer frame removal step of removing an outer frame edge of the lead frame raw material 11 with a plating burr 37 by press working, and a pilot hole formation step of forming pilot holes 29 in a region except the unit lead frame regions 10 of the lead frame raw material 11 by press working.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供制造半导体器件的半导体器件和引线框架的方法，其中由蚀刻产生的任何电镀毛刺都不在用作产品的引线框架中，也不在半导体器件中。解决方案：该方法用于在引线框架原料11中的每个单元引线框区域10上制造半导体器件12，其中多个单元引线框架区域10布置在多个列或单个列，其中，通过使用第一镀层24作为抗蚀剂膜，从其前侧对引线框架原料11进行半蚀刻，提供了一种外框除去步骤，用于除去引线框架原料11的外框边缘，通过冲压加工的电镀毛刺37，以及通过冲压加工在引线框架原料11的单位引线框架区域10之外的区域中形成引导孔29的引导孔形成步骤。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2013033822A Lead frame, manufacturing method of lead frame, and semiconductor device using lead frame 有权
标题翻译：引线框架，引线框架的制造方法和使用引线框架的半导体器件
公开(公告)号：JP2013033822A
公开(公告)日：2013-02-14
申请号：JP2011168599
申请日：2011-08-01
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： SHIMIZU KOJI , MITSUI MASANORI
IPC分类号： H01L23/50
CPC分类号： H01L23/4951 , H01L21/4842 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L24/03 , H01L2224/48091 , H01L2224/48247 , H01L2924/12042 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a lead frame which prevents resin burrs from adhering to a die pad in a semiconductor device where the die pad is exposed from a bottom surface, a manufacturing method of the lead frame, and the semiconductor device using the lead frame.SOLUTION: In a lead frame 10 used in a semiconductor device 20 where a rear surface of a die pad 11 having a semiconductor element 21 mounted thereon is exposed, first metal burrs 16 protruding in a direction of a package lower surface are formed at an outer peripheral part on the rear surface of the die pad 11, and a tip of each first metal burr 16 is flat. Further, multiple external terminals 26 having the same surfaces as the rear surface of the die pad 11 are formed around the die pad 11. Second metal burrs 27 protruding in the direction of the package lower surface are formed at terminal outer peripheral parts of the multiple external terminals 26, and a tip of each metal burr 27 is flat.
摘要翻译：要解决的问题：提供一种引线框架，其防止树脂毛刺粘附到芯片基板从底面露出的半导体器件中的管芯焊盘，引线框架的制造方法和半导体器件使用引线框架。解决方案：在半导体器件20中使用的引线框架10中，其中安装有半导体元件21的管芯焊盘11的后表面被暴露，形成在封装下表面的方向上突出的第一金属毛刺16 在芯片垫11的后表面的外周部分，并且每个第一金属毛刺16的末端是平坦的。此外，具有与芯片焊盘11的背面相同的表面的多个外部端子26形成在芯片焊盘11周围。在封装下表面的方向上突出的第二金属毛刺27形成在多个端子的外围部分外部端子26，并且每个金属毛刺27的末端是平坦的。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2012227329A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012227329A
公开(公告)日：2012-11-15
申请号：JP2011093040
申请日：2011-04-19
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： SHIMIZU KOJI , NARIMATSU HIROAKI
IPC分类号： H01L23/50
CPC分类号： H01L2224/45144 , H01L2224/48247 , H01L2224/49171 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can reduce a length of a bonding wire and increase an interval of inner leads and neighboring connection terminals connected to the inner leads.SOLUTION: A semiconductor device 10 comprises a semiconductor element 13 mounted on an element mounting part 12 and provided at the center in a resin encapsulated package 11, and a plurality of connection terminals 15 arranged side by side on the inside of side edges of the package 11 and exposed on a rear face. Each of the connection terminals 15 are electrically connected with the electrode parts of the semiconductor element 13. An inner lead 19 extends from each connection terminal 15, and a relay terminal 21 is provided at an intermediate position of an electrode part of the semiconductor element 13 corresponding to an inner end 20 of the inner lead 19. The electrode part and the relay terminal 21 are linked by a first bonding wire 28 and the relay terminal 21 and the inner end 20 are linked by a second bonding wire 29.
摘要翻译：解决的问题：为了提供一种半导体器件及其制造方法，其可以减小接合线的长度并增加内引线和连接到内引线的相邻连接端的间隔。解决方案：半导体器件10包括安装在元件安装部分12上并设置在树脂密封封装11的中心处的半导体元件13和在侧边缘的内侧并排布置的多个连接端子15 并暴露在背面上。每个连接端子15与半导体元件13的电极部分电连接。内引线19从每个连接端子15延伸，并且中继端子21设置在半导体元件13的电极部分的中间位置对应于内引线19的内端20.电极部分和中继端子21通过第一接合线28和中继端子21连接，并且内端20通过第二接合线29连接。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2010283246A Lead frame and semiconductor device 有权
标题翻译：引线框架和半导体器件
公开(公告)号：JP2010283246A
公开(公告)日：2010-12-16
申请号：JP2009136799
申请日：2009-06-08
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： SHIMIZU KOJI
IPC分类号： H01L23/50 , H01L23/28
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents the short-circuit of a lead caused by metallic burrs, generated when a semiconductor device sealed with resin collectively is diced by a rotary blade and a lead frame used for this.
SOLUTION: In a lead frame in which a unit lead frame is arranged in such a manner that the unit lead frame is lined up in a matrix shape and the rear surface of a portion for mounting a semiconductor element and the rear surface of a lead which is not subjected to a thinning process are exposed, the distance to an adjacent lead is not equal.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体装置，其防止当由用于此的旋转刀片和引线框切割用树脂密封的半导体器件时产生的由金属毛刺引起的引线的短路。解决方案：在引线框架中，单元引线框架以这样的方式布置，使得单元引线框架以矩阵形状排列，并且用于安装半导体元件的部分的后表面和没有经历变薄处理的引线被暴露，到相邻引线的距离不相等。版权所有（C）2011，JPO＆INPIT

7. 发明专利

JP2010129591A Lead frame, semiconductor device using the lead frame and intermediate product thereof, and method for manufacturing same 审中-公开
标题翻译：引线框架，使用引线框架的半导体器件及其中间产品及其制造方法
公开(公告)号：JP2010129591A
公开(公告)日：2010-06-10
申请号：JP2008299726
申请日：2008-11-25
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： SHIMIZU KOJI , YAGAWA HIROAKI
IPC分类号： H01L23/50
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2224/85444 , H01L2924/00014 , H01L2924/01004 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a lead frame which enables obtaining a reliable semiconductor device, by improving the adhesion between a terminal and sealing resin, and to provide a semiconductor device that uses the lead frame and an intermediate product thereof, and to provide a method for manufacturing them. SOLUTION: In the lead frame for a semiconductor device 10, with a plurality of terminals 13 in which one side is sealed with resin, a part 16 of the terminal 13 to be sealed with resin is in the shape of a polygonal pillar of five or more angles, or in the shape of odd-form pillar which has one or more notches or trenches along a vertical direction around the part. The formation of the part 16 to be sealed with resin is performed by etching processing or press working, and the formation of an exposed part 18 in the lower half of the terminal 13 is performed by etching processing. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够通过改善端子和密封树脂之间的粘附性而获得可靠的半导体器件的引线框架，并提供使用引线框架及其中间产品的半导体器件，以及以提供制造它们的方法。解决方案：在半导体器件10的引线框架中，在其中一侧用树脂密封的多个端子13中，用树脂密封的端子13的部分16为多边形柱状或者具有沿着垂直方向围绕该部分的一个或多个凹口或沟槽的奇数形状的支柱的形状。用树脂密封的部分16的形成是通过蚀刻加工或冲压加工进行的，并且通过蚀刻处理在端子13的下半部中形成暴露部分18。版权所有（C）2010，JPO＆INPIT

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