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1. 发明专利

JP2007048981A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007048981A
公开(公告)日：2007-02-22
申请号：JP2005232452
申请日：2005-08-10
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： TAKAI KEIJI , HIRASHIMA TETSUYUKI
IPC分类号： H01L23/12 , H01L23/50
CPC分类号： H01L2224/16245 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/01078 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which defective products are reduced by removing plating burrs occurred in etching processing. SOLUTION: The method for manufacturing a semiconductor device includes: a first step for forming plating masks 13 and 14 corresponding to an internal connection terminal 17 and an external connection terminal 22; a second step for projecting the internal connection terminal 17 by performing etching processing of a predetermined depth using the plating mask 13 on the surface as a resist mask; a third step for mounting a semiconductor element 18 and connecting its electrode pads 30, respectively, with corresponding internal connection terminals 17; a fourth step for resin-sealing the semiconductor element 18 and the internal connection terminals 17; and a fifth step for projecting the external connection terminal 22 by performing etching processing on the backside, wherein plating burrs 26 at the internal connection terminal 17 and the external connection terminal 22 are removed after second step and fifth step, respectively. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体器件的方法，其中通过去除在蚀刻处理中发生的电镀毛刺而减少有缺陷的产品。解决方案：半导体器件的制造方法包括：形成对应于内部连接端子17和外部连接端子22的电镀掩模13和14的第一步骤; 通过使用表面上的电镀掩模13作为抗蚀剂掩模进行预定深度的蚀刻处理来投射内部连接端子17的第二步骤; 安装半导体元件18并将其电极焊盘30分别连接到相应的内部连接端子17的第三步骤; 用于树脂密封半导体元件18和内部连接端子17的第四步骤; 以及第五步骤，通过在背面执行蚀刻处理来投射外部连接端子22，其中分别在第二步骤和第五步骤之后，在内部连接端子17和外部连接端子22处的电镀毛刺26被去除。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2008227410A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008227410A
公开(公告)日：2008-09-25
申请号：JP2007067317
申请日：2007-03-15
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： TAKAI KEIJI , HIRASHIMA TETSUYUKI , MIMURA SHINYA
IPC分类号： H01L23/12 , H01L23/50
CPC分类号： H01L2224/48247 , H01L2224/49171 , H01L2924/3025 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a long joining terminal directly connected to an element mounting part around an element mounting part, capable of improving workability of a bonding wire, and having a sufficient resistance to a deformation. SOLUTION: A semiconductor device 10 includes a bonding wire 17 connecting a plurality of terminal conductors 14 arranged like a grid array around an element mounting part 11, with a wire bonding terminal 12 provided in the upper part and a first connection terminal 13 provided in the lower part, a semiconductor element 15 mounted on the element mounting part 11, and a wire bonding terminal 12 corresponding to each electrode pad 16 of the semiconductor element 15; and a sealing resin 18 bespreading the upper side of the element mounting part 11 and the semiconductor element 15 mounted thereon, the bonding wire 17, and at least the upper half part of the terminal conductor 14. In this semiconductor device 10, a long joining terminal 19 of the same height as that of the wire bonding terminal 12 is provided around the element mounting part 11. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体器件，其具有直接连接到元件安装部件周围的元件安装部分的长接合端子，能够提高接合线的加工性，并且具有足够的变形阻力。解决方案：半导体器件10包括：接合线17，其连接多个端子导体14，该多个端子导体14围绕元件安装部分11布置成格栅阵列;以及设置在上部的引线接合端子12和第一连接端子13 设置在下部，安装在元件安装部11上的半导体元件15和与半导体元件15的每个电极焊盘16对应的引线键合端子12; 以及封装元件安装部分11的上侧和安装在其上的半导体元件15，接合线17以及端子导体14的至少上半部分的密封树脂18.在该半导体器件10中，端子19与引线接合端子12的高度相同，设置在元件安装部分11周围。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2008071815A Semiconductor device and lead frame product for use in semiconductor device and process for manufacturing semiconductor device 有权
标题翻译：用于半导体器件的半导体器件和引线框架产品及制造半导体器件的工艺
公开(公告)号：JP2008071815A
公开(公告)日：2008-03-27
申请号：JP2006246990
申请日：2006-09-12
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： MATSUNAGA KIYOSHI , SHIOYAMA TAKAO , HIRASHIMA TETSUYUKI
IPC分类号： H01L23/50 , H01L23/12 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L23/3107 , H01L21/4832 , H01L21/6835 , H01L23/49537 , H01L23/49541 , H01L23/49582 , H01L24/28 , H01L24/48 , H01L24/49 , H01L24/83 , H01L24/85 , H01L25/105 , H01L2221/68377 , H01L2224/131 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/484 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/83851 , H01L2224/85001 , H01L2224/85439 , H01L2224/85444 , H01L2225/1029 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/19043 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a multilayer multichip modular semiconductor device, a lead frame product for use in the semiconductor device, and a process for manufacturing the semiconductor device. SOLUTION: The semiconductor device 10 has a semiconductor element 12, a group of inner back side terminals 14 coupled with the semiconductor element 12 through a bonding wire 13 and arranged in area array while being exposed to the inside of the footprint, a group of outer back side terminals 15 formed on the outside of the group of inner back side terminals 14 contiguously thereto, a group of outer surface side terminals 17 located directly above the outer back side terminals 15 while being exposed to the surface and coupled electrically with the outer back side terminals 15 directly under through a coupling conductor 16, and resin 18 for sealing the unexposed part of the semiconductor element 12, the bonding wire 13, each inner back side terminal 14, each outer back side terminal 15 and each outer surface side terminal 17 wherein noble metal plating layers 19 and 19b are formed on the respective terminal surfaces of at least the inner back side terminal 14, the outer back side terminal 15 and the outer surface side terminal 17. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种多层多芯片模块化半导体器件，用于半导体器件的引线框架产品以及半导体器件的制造工艺。解决方案：半导体器件10具有半导体元件12，一组内侧侧端子14，其通过接合线13与半导体元件12耦合，并且在暴露于占位面的内部的同时以面阵列布置，一组外侧端子15，形成在与其相邻的内侧后端子端子组14的外侧;一组外表面侧端子17，位于外侧端子15的正上方，同时暴露于表面并与通过耦合导体16正下方的外侧背面端子15以及用于密封半导体元件12的未曝光部分，接合线13，内侧后端子端子14，各外侧后端子端子15以及各外表面的树脂18 侧端子17，其中贵金属镀层19和19b形成在至少内侧后端子端子14，外侧背面端子小号15和外表面侧终端17.版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2007157846A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2007157846A
公开(公告)日：2007-06-21
申请号：JP2005348239
申请日：2005-12-01
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： MATSUNAGA KIYOSHI , SHIOYAMA TAKAO , TAKAI KEIJI , HIRASHIMA TETSUYUKI , MIMURA SHINYA , TSUJIMOTO KEIICHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device with no polishing after resin coating required, capable of forming an effective electrode terminal at the lower part of a semiconductor element depending on cases, with a relatively simple manufacturing method. SOLUTION: Front and rear side wiring patterns 26 and 27 are formed on both sides of a lead frame material 23, using first and second resist films 24 and 25, with anti-etching plating 20 and 21 applied on the exposed portions. The second resist film 25 on the rear surface side is removed for half-etching, and a recess 29 that has been half-etched is injected with a resin 19. The front surface side of the lead frame material 23 is etched with the anti-etching plating 20 as a resist film, so that a lead frame base 12 is formed comprising joint terminals 14 and 14a and a lead 17. A semiconductor element 13 is mounted on the lead frame base 12, and the entire is resin-sealed after wire bonding. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决方案：提供一种制造半导体器件的方法，该半导体器件在需要树脂涂层之后不进行抛光，能够根据情况在半导体元件的下部形成有效电极端子，以相对简单的制造方法。解决方案：使用第一和第二抗蚀剂膜24和25，在引线框架材料23的两侧上形成前和后侧布线图案26和27，其中施加有暴露部分的抗蚀刻镀层20和21。背面侧的第二抗蚀剂膜25被去除以进行半蚀刻，并且用树脂19注入半蚀刻的凹部29.引线框架材料23的前表面侧用抗蚀剂蚀刻电镀20作为抗蚀剂膜，从而形成包括接合端子14和14a以及引线17的引线框架基座12.半导体元件13安装在引线框架基座12上，并且在导线之后树脂密封结合。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2012049323A Lead frame and semiconductor device using the same and method of manufacturing the same 审中-公开
标题翻译：使用其的引线框架和半导体器件及其制造方法
公开(公告)号：JP2012049323A
公开(公告)日：2012-03-08
申请号：JP2010189797
申请日：2010-08-26
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： MATSUNAGA KIYOSHI , SHIOYAMA TAKAO , HIRASHIMA TETSUYUKI
IPC分类号： H01L23/50 , H01L23/12
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a lead frame which can minimize degradation in quality of a product by preventing a terminal from coming out of resin, and to provide a method of manufacturing the same.SOLUTION: A lead frame 16 is provided, on one side thereof, with a wire bonding portion 13 having a first plating part 12 formed on the surface and, on the other side thereof, with an external connection terminal 15 corresponding to the wire bonding portion 13 and having a second plating part 14 formed on the surface. The first plating part 12 is projected from around the tip of the wire bonding portion 13 and the thickness T1 of the first plating part 12 excepting a noble metal plating layer is set in the range of 5-50 μm before forming a first stopper 23 around the tip of the wire bonding portion 13. In the manufacturing method, the first plating part 12 is formed by applying thick plating 26 to the pointed end face of a wire bonding portion 13 to be formed, and then etching a lead frame material 20. A semiconductor device 10 uses this lead frame 16.
摘要翻译：要解决的问题：提供一种引线框架，其可以通过防止端子从树脂中脱出而使产品的质量降低最小化，并提供其制造方法。解决方案：引线框架16的一侧设置有引线接合部分13，引线接合部分13具有形成在表面上的第一电镀部分12，并且在另一侧具有对应于外部连接端子15的外部连接端子15。引线接合部分13并且具有形成在表面上的第二电镀部分14。第一电镀部12从引线接合部13的前端突出，除了贵金属电镀层之外，第一电镀部12的厚度T1在形成第一止动件23之前设定在5-50μm的范围内导线接合部分13的尖端。在制造方法中，通过将厚镀层26施加到待形成的引线接合部分13的尖端面上，然后蚀刻引线框架材料20来形成第一电镀部分12。半导体器件10使用该引线框架16.版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2005026628A Semiconductor device packaging method 有权
标题翻译：半导体器件封装方法
公开(公告)号：JP2005026628A
公开(公告)日：2005-01-27
申请号：JP2003270782
申请日：2003-07-03
申请人： Mitsui High Tec Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社三井ハイテック
发明人： WATANABE TOMOYUKI , EDA AKINORI , MORITA TAKESHI , YAMAGUCHI KAZUTOSHI , SHIOYAMA TAKAO , HIRASHIMA TETSUYUKI
IPC分类号： H01L21/52
CPC分类号： H01L24/32 , H01L24/743 , H01L24/83 , H01L2224/32225 , H01L2224/743 , H01L2224/83 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To highly accurately control a packaging position while suppressing costs low in a semiconductor device packaging method for packaging a semiconductor device on a substrate by soldering.
SOLUTION: The semiconductor device packaging method for packaging a semiconductor device 2 on the substrate by soldering includes the steps of: setting the semiconductor device 2 on a substrate 1 on which a fixing tape 5 is stuck, and temporarily fixing the packaging position of the semiconductor device 2 using the fixing tape 5; pressing the fixing tape 5 to solder foil thickness and thermosetting the fixing tape by press-welding the set semiconductor device 2 onto the substrate 1; and soldering the semiconductor device 2 and the substrate 1 using reflowing.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了在通过焊接将半导体器件封装在衬底上的半导体器件封装方法中抑制成本低的同时高度准确地控制封装位置。解决方案：通过焊接将半导体器件2封装在衬底上的半导体器件封装方法包括以下步骤：将半导体器件2设置在其上固定有固定带5的衬底1上，并临时固定封装位置使用固定带5的半导体器件2; 按压固定带5以焊接箔厚度并通过将设置的半导体器件2压焊到衬底1上来固化固定带; 以及使用回流焊接半导体器件2和衬底1。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2007048978A Semiconductor device and method for manufacturing same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007048978A
公开(公告)日：2007-02-22
申请号：JP2005232428
申请日：2005-08-10
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： TAKAI KEIJI , HIRASHIMA TETSUYUKI
IPC分类号： H01L23/12
CPC分类号： H01L2224/48091 , H01L2924/01078 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which defective products are reduced by preventing the occurrence of plating burrs. SOLUTION: In the method for manufacturing a semiconductor device 28 by: forming plating masks 38 and 39 having a noble metal plating layer 35 as an uppermost layer at a predetermined part on the surface or the backside of a lead frame material 10; etching the lead frame material 10 sequentially using the plating masks 38 and 39 as a resist mask and conducting it electrically with a semiconductor element 18 arranged in a sealing resin 21; and then forming a projecting external connection terminal 22 at a lower portion, wherein lowermost layer of the plating masks 38 and 39 includes base metal plating or noble metal plating 33 exhibiting etching liquid resistance. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，其中通过防止电镀毛刺的发生而减少有缺陷的产品。解决方案：在半导体器件28的制造方法中，通过以下方式形成：在引线框架材料10的表面或背面上的预定部分处形成具有贵金属镀层35作为最上层的电镀掩模38和39; 使用电镀掩模38和39作为抗蚀剂掩模，依次对引线框架材料10进行蚀刻，并将其与布置在密封树脂21中的半导体元件18电连接; 然后在下部形成突出的外部连接端子22，其中电镀掩模38和39的最下层包括呈现抗蚀刻液体电阻的基底金属电镀或贵金属电镀33。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2003332511A Lead frame and semiconductor device 有权
标题翻译：引线框架和半导体器件
公开(公告)号：JP2003332511A
公开(公告)日：2003-11-21
申请号：JP2002134376
申请日：2002-05-09
申请人： Mitsui High Tec Inc , 株式会社三井ハイテック
发明人： MIMURA SHINYA , HIRASHIMA TETSUYUKI , KAWAMURA HIROKI , MORITA TAKESHI
IPC分类号： H01L21/56 , H01L23/50
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2224/85001 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent an external appearance from increasing in vain and improve mounting density, and a lead frame which can prevent an external appearance from increasing in vain in a semiconductor device and improve mounting density in the semiconductor device.
SOLUTION: The semiconductor device 1 which is an embodiment in this invention is manufactured by using a lead frame 10 which stretches parallel with the side 12a of a tie bar 12 from corners 11c of a die pad 11, and makes the tie bar 12 retain the die pad 11 by support bars 14 connected with positions isolated from the corners 12c of the tie bar 12. The lead frame 10 which is an embodiment in this invention stretches parallel with the side 12a of the tie bar 12 from the corners 11c of the die pad 11, and makes the tie bar 12 retain the die pad 11 by the support bars 14 connected with positions isolated from the corners 12c of the tie bar 12.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种能够防止外观增加并提高安装密度的半导体器件，以及能够防止外部因外界在半导体器件中的增加而引起的引线框架，并提高安装密度在半导体器件中。解决方案：作为本发明实施例的半导体器件1通过使用引线框架10制造，该引线框架10从连接杆12的侧面12a平行于管芯焊盘11的角部11c并且使连接杆 12通过与从连接杆12的角部12c分离的位置连接的支撑杆14来保持管芯焊盘11.作为本发明实施例的引线框架10从连接杆12的侧面12a平行于角部11c 并且使得连接杆12通过与从连接杆12的角部12c隔开的位置连接的支撑杆14来保持模具垫11.版权所有（C）2004，JPO

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