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1. 发明专利

JP2014057026A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2014057026A
公开(公告)日：2014-03-27
申请号：JP2012202468
申请日：2012-09-14
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KITANI TAKESHI , TARUI YOICHIRO
IPC分类号： H01L29/47 , H01L21/20 , H01L21/329 , H01L29/06 , H01L29/861 , H01L29/868 , H01L29/872
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0692 , H01L29/1608 , H01L29/36
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which can achieve sufficient withstand voltage by less number of ion injections.SOLUTION: A silicon carbide semiconductor device comprises: a silicon carbide drift layer 1 formed on a silicon carbide substrate 10; a P-type region 2 formed in a surface layer of the silicon carbide drift layer 1; and a Schottky electrode 3 formed on the silicon carbide drift layer 1 depending on a formation part of the P-type region 2. The P-type region 2 is formed by arranging a plurality of unit cells 20 each of which is a repetition unit of a P-type impurity distribution. Each unit cell 20 includes at least a first distribution region 20A where the P-type impurity is distributed at a first concentration and a second distribution region 20B where the P-type impurity is distributed at a second concentration higher than the first concentration.
摘要翻译：要解决的问题：提供一种能够通过较少数量的离子注入实现足够的耐受电压的碳化硅半导体器件。解决方案：碳化硅半导体器件包括：形成在碳化硅衬底10上的碳化硅漂移层1; 形成在碳化硅漂移层1的表面层中的P型区域2; 以及根据P型区域2的形成部分形成在碳化硅漂移层1上的肖特基电极3.P型区域2通过布置多个单元电池20而形成，每个单元电池20是重复单元 P型杂质分布。每个单元电池20至少包括第一分配区域20A，其中P型杂质以第一浓度分布;以及第二分布区域20B，其中P型杂质以比第一浓度高的第二浓度分布。

2. 发明专利

JP2012178494A Silicon-carbide junction barrier schottky diode and manufacturing method thereof 有权
标题翻译：硅碳双绞线肖特基二极管及其制造方法
公开(公告)号：JP2012178494A
公开(公告)日：2012-09-13
申请号：JP2011041223
申请日：2011-02-28
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OKUNO KOJI , TARUI YOICHIRO
IPC分类号： H01L29/47 , H01L21/329 , H01L29/06 , H01L29/861 , H01L29/868 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To selectively form a pregion on a p-well and to reduce contact resistance of a metal electrode and the pregion without using a hard mask in manufacturing a silicon-carbide junction barrier Schottky diode.SOLUTION: A pregion 4 is formed over an entire upper portion of an n-type epitaxial layer 2 by high-temperature ion implantation, and an n-type region below the pregion 4a is partially exposed by selectively etching the pregion 4a, thereby forming a psemiconductor projection 4 which is protruded upward from an upper surface of the n-type region. An anode electrode is formed to cover the exposed portion of the n-type region and the psemiconductor projection 4.
摘要翻译：要解决的问题：选择性地在p阱上形成ap + 区域并降低金属电极的接触电阻，并且p + 区域，而不使用硬掩模制造碳化硅结屏障肖特基二极管。解决方案：通过高温离子注入在n型外延层2的整个上部上形成p + 区域4，并且n型区域通过选择性地蚀刻p + 区域4a来部分地露出p + 区域4a，由此形成ap + 半导体突起4的露出部分。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012129492A Silicon carbide semiconductor device and method of manufacturing the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012129492A
公开(公告)日：2012-07-05
申请号：JP2011161585
申请日：2011-07-25
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO , SHIKAGUCHI NAOTO , NAKAMURA TAKUYO
IPC分类号： H01L29/12 , H01L21/336 , H01L29/06 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/046 , H01L29/0615 , H01L29/0619 , H01L29/1095 , H01L29/66068 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To increase the margin of the amount of etching for removing a damage layer occurring on a surface of a termination region in manufacturing a silicon carbide semiconductor device having the termination region that is a JTE region or a FLR.SOLUTION: A silicon carbide semiconductor device has a termination region that is a junction termination extension (JTE) region or a field limiting ring (FLR) at the termination portion of a semiconductor element. The termination region is formed by single-step ion injection in which the kind of impurity and injection energy are fixed. In the impurity concentration profile in the depth direction of the termination region, the concentration peak in the shallowest position is located at the position deeper than 0.35 μm from the surface and the concentration of the surface portion is one-tenth or less of the concentration peak in the shallowest position.
摘要翻译：要解决的问题：在制造具有作为JTE区域或FLR的终止区域的碳化硅半导体器件的情况下，增加用于去除终止区域表面上出现的损伤层的蚀刻量的余量。解决方案：碳化硅半导体器件具有作为半导体元件的端接部分处的结端接延伸（JTE）区域或场限制环（FLR）的端接区域。通过单步离子注入形成终止区域，其中固定了杂质和注入能量的种类。在终止区域的深度方向的杂质浓度分布中，最浅位置的浓度峰位于距表面0.35μm以下的位置，表面部分的浓度为浓度峰值的十分之一以下在最浅的位置。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2012104648A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012104648A
公开(公告)日：2012-05-31
申请号：JP2010251725
申请日：2010-11-10
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7802 , H01L23/544 , H01L29/0657 , H01L29/0878 , H01L29/1608 , H01L29/167 , H01L29/41766 , H01L29/42368 , H01L29/66068 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of relaxing an electric field and capable of suppressing gate capacitance, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device of the present invention comprises: a first-conductive-type semiconductor substrate 1; a first-conductive-type epitaxial layer 23 that is formed on the semiconductor substrate 1 and has a salient on its surface; second-conductive-type well regions 3 formed on the surface of the epitaxial layer 23 so as to sandwich the salient; first-conductive-type source regions 4 selectively formed on surfaces of the well regions 3; a gate insulating film 6 formed so as to cover at least the salient and the well regions 3; and a gate electrode 7 formed on the gate insulating film 6 corresponding to the salient. In the gate insulating film 6, the thickness of the region corresponding to the top surface of the salient is thicker than that of the other regions.
摘要翻译：解决的问题：提供一种能够放松电场并能够抑制栅极电容的半导体器件，并提供其制造方法。解决方案：本发明的半导体器件包括：第一导电型半导体衬底1; 第一导电型外延层23，其形成在半导体基板1上并且在其表面上具有凸面; 形成在外延层23的表面上的第二导电型阱区3，以便夹着突出部; 选择性地形成在阱区域3的表面上的第一导电型源极区域4; 形成为至少覆盖凸部和阱区域3的栅极绝缘膜6; 以及形成在栅极绝缘膜6上的与显着对应的栅电极7。在栅极绝缘膜6中，与突出部的顶面对应的区域的厚度比其他区域的厚度厚。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2009076930A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009076930A
公开(公告)日：2009-04-09
申请号：JP2008290576
申请日：2008-11-13
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , TARUI YOICHIRO , IMAIZUMI MASAYUKI , SUGIMOTO HIROSHI , TAKAMI TETSUYA
IPC分类号： H01L29/06 , H01L21/28 , H01L27/04 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a high withstand voltage, a low on-resistance and hard-to-deteriorate element property.
SOLUTION: The semiconductor device includes a n-type substrate 1, a n-type drift layer 2 formed on the n-type substrate 1, a n-type semiconductor layer 4a, a plurality of p-type base regions 5 isolated from one another at predetermined spaces, a n-type source region 6 formed in each of the base regions 5, a source electrode 10 provided on the surface of part of each of the source regions 6, gate electrodes 8 provided on the surface of part of each of the source regions 6 and on the surface of the n-type semiconductor layer 4a between the source regions 6 via gate insulating films. The n-type semiconductor layer 4a is constructed as a single layer. Impurity concentration N
1 of the n-type drift layer 2 and impurity concentration N
s of the n-type semiconductor layer 4a have a relationship of N
s 1 . A second conductivity type guard ring region is provided in the semiconductor layer at a site encircling the plurality of base regions with one end contacting the base regions.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供具有高耐受电压，低导通电阻和难以劣化的元件特性的半导体器件。解决方案：半导体器件包括n型衬底1，形成在n型衬底1上的n型漂移层2，n型半导体层4a，隔离的多个p型基极区域5 在每个基区5中形成的n型源区6，设置在每个源极区6的一部分的表面上的源电极10，设置在部分的表面上的栅电极8 并且经由栅极绝缘膜在源极区域6之间的n型半导体层4a的表面上。 n型半导体层4a构成为单层。 n型漂移层2的杂质浓度N 1 和n型半导体层4a的杂质浓度N s 具有N < SB> 1 。第二导电型保护环区域设置在半导体层中的环绕多个基极区域的位置处，其一端接触基极区域。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008270308A Process for fabricating silicon carbide semiconductor device 有权
标题翻译：制备碳化硅半导体器件的方法
公开(公告)号：JP2008270308A
公开(公告)日：2008-11-06
申请号：JP2007107720
申请日：2007-04-17
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO , SAWADA TAKAO
IPC分类号： H01L29/78 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a process for fabricating a silicon carbide semiconductor device in which a CNT can be formed selectively by short-time treatment under low temperature without using a fine particle catalyst. SOLUTION: The process for fabricating a silicon carbide semiconductor device comprises (a) a step for making the surface of SiC 1 amorphous by introducing impurities, (b) a step for forming a CNT 5 on the surface of amorphous SiC 3 by heat treatment, and (c) a step for forming a CNT 5 further thereon by using the CNT 5 as a ground. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造碳化硅半导体器件的方法，其中通过在低温下短时间处理可以选择性地形成CNT，而不使用细颗粒催化剂。解决方案：制造碳化硅半导体器件的工艺包括（a）通过引入杂质使SiC 1的表面无定形的步骤，（b）在非晶SiC 3的表面上形成CNT 5的步骤，通过热处理，以及（c）通过使用CNT 5作为地面，进一步在其上形成CNT 5的工序。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2007066959A Process for fabricating silicon carbide semiconductor device 审中-公开
标题翻译：制备碳化硅半导体器件的方法
公开(公告)号：JP2007066959A
公开(公告)日：2007-03-15
申请号：JP2005247401
申请日：2005-08-29
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： WATANABE TOMOKATSU , TARUI YOICHIRO , IMAIZUMI MASAYUKI , OTSUKA KENICHI , TAKAMI TETSUYA
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a process for fabricating a silicon carbide semiconductor device in which the problems of aggregation of impurities, and the like, are eliminated in a silicon carbide layer, etching of a base contact portion is suppressed in activated annealing, or the like, and low resistivity ohmic contact is established between the source-base common electrode and the base contact portion. SOLUTION: A base contact portion 15 is formed by implanting Al ions at an impurity concentration of 2e20 cm -3 while holding the substrate temperature between 400-800°C. When ions are implanted while holding the substrate temperature between 400-800°C, crystallinity aggravation of a silicon carbide layer is suppressed when ions are implanted, problems of aggregation of impurities, and the like, are eliminated in a silicon carbide layer and etching of the base contact portion 15 is suppressed in activated annealing, or the like. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种制造碳化硅半导体器件的方法，其中在碳化硅层中消除了杂质聚集等问题，抑制了基极接触部分的腐蚀被激活退火等，并且在源极公共电极和基极接触部分之间建立低电阻率的欧姆接触。解决方案：通过在保持衬底温度在400-800℃之间的情况下，以2e20cm 3的浓度注入Al离子形成基底接触部分15。当保持衬底温度在400-800℃之间时注入离子时，当注入离子时，抑制碳化硅层的结晶度恶化，在碳化硅层中消除杂质聚集等问题，并蚀刻碱性接触部分15在活化退火中被抑制等。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2004363398A Semiconductor device 有权
公开(公告)号：JP2004363398A
公开(公告)日：2004-12-24
申请号：JP2003161154
申请日：2003-06-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： IMAIZUMI MASAYUKI , FUJIHIRA KEIKO , TARUI YOICHIRO , SUGIMOTO HIROSHI , OTSUKA KENICHI , TAKAMI TETSUYA
IPC分类号： H01L29/06 , H01L21/04 , H01L21/336 , H01L29/12 , H01L29/24 , H01L29/739 , H01L29/78 , H01L29/861 , H01L31/10
CPC分类号： H01L29/66068 , H01L21/045 , H01L29/1608 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a satisfactory characteristic by decreasing a density of an electric charge trap level which is a center of the electric charge trap. SOLUTION: The semiconductor device comprises silicon carbides 2, 3, 4 on which a vertical type MOSFET is formed, and oxide film 6 and antioxidant layer 5 formed on the silicon carbides 2, 3, 4. The antioxidant layer 5 is formed between the silicon carbides 2, 3, 4 and the oxide film 6 to prevent an oxidation of the silicon carbides 2, 3, 4. COPYRIGHT: (C)2005,JPO&NCIPI

9. 发明专利

JP2013258287A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2013258287A
公开(公告)日：2013-12-26
申请号：JP2012133337
申请日：2012-06-13
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OKUNO KOJI , TARUI YOICHIRO
IPC分类号： H01L21/266 , H01L21/329 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/868 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can prevent collapse of a line-shaped resist.SOLUTION: A semiconductor device manufacturing method comprises: forming on a semiconductor substrate 10, a resist pattern including line-shaped resists which surround an effective region 101; and ion implanting an impurity to the semiconductor substrate 10 by using the resist pattern as a mask to form a FLR (Field Limiting Ring). The resist pattern includes projections which locally project from lateral faces of the line-shaped resists and do not connect to parts other than the line-shaped resists.
摘要翻译：要解决的问题：提供一种能够防止线状抗蚀剂塌陷的半导体器件制造方法。解决方案：半导体器件制造方法包括：在半导体衬底10上形成抗蚀剂图案，该抗蚀剂图案包括线状抗蚀剂，有效区域101; 以及通过使用抗蚀剂图案作为掩模将杂质注入到半导体衬底10中以形成FLR（场限制环）。抗蚀剂图案包括从线状抗蚀剂的侧面局部突出并且不连接到除了线状抗蚀剂之外的部分的突起。

10. 发明专利

JP2010245389A Silicon carbide semiconductor device and manufacturing method thereof 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2010245389A
公开(公告)日：2010-10-28
申请号：JP2009094020
申请日：2009-04-08
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO
IPC分类号： H01L29/12 , H01L21/336 , H01L29/78
CPC分类号： H01L21/0455 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/66068
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon carbide semiconductor device which can relax an electric field applied to a gate oxide film, and thereby can ensure reliability of the gate oxide film and can also prevent increase of the manufacturing cost, as much as possible.
SOLUTION: If the lengths extended to a depletion region, with respect to the inner sides of source regions, of each of well regions, channel regions and gate electrodes are defined as Lwell, Lch and Lg, respectively, the well regions, the channel regions and the gate electrodes are formed, in such a way that a relationship of Lch
摘要翻译：解决的问题：提供一种可以使施加到栅极氧化膜的电场放松的碳化硅半导体器件的制造方法，从而可以确保栅极氧化膜的可靠性，并且还可以防止制造的增加成本，尽可能多。解决方案：如果将各个阱区域，沟道区域和栅极电极相对于源极区域的内侧延伸到耗尽区的长度分别定义为Lwell，Lch和Lg，则阱区域，以满足Lch

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